Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

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ID 730783
Date 5/13/2024
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Document Table of Contents
Document Table of Contents x
1. About the RiscFree* IDE 2. Installation and Setup 3. Getting Started with RiscFree* IDE 4. Debug Setup for Nios® V Processor System 5. Debug Setup for Arm* Hard Processor System 6. Debugging with RiscFree* IDE 7. Debugging with Command-Line Interface 8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives 9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide A. Appendix
1. About the RiscFree* IDE x
1.1. Supported Devices 1.2. Quartus® Prime Software Support 1.3. Intel® Simics® Simulator for Intel® FPGAs Support
2. Installation and Setup x
2.1. Bundled Installation with the Quartus® Prime Software 2.2. Standalone Installation
2.2. Standalone Installation x
2.2.1. Standalone Installation with Supported Quartus® Prime Software 2.2.2. Standalone Installation with the Quartus® Prime Programmer and Tools
3. Getting Started with RiscFree* IDE x
3.1. Graphical User Interface 3.2. Command Line Interface 3.3. Ashling* RiscFree* IDE for Intel® FPGAs Interaction with Intel® Simics® Simulator for Intel® FPGAs
4. Debug Setup for Nios® V Processor System x
4.1. Importing Nios® V Processor Project 4.2. Building Nios® V Processor Project 4.3. Setting Debug Configurations and Downloading Nios® V Processor Project Using RiscFree* IDE
5. Debug Setup for Arm* Hard Processor System x
5.1. Pre-requisite for Debugging Arm* HPS Project 5.2. Importing Arm* HPS Project 5.3. Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE
6. Debugging with RiscFree* IDE x
6.1. Debug Features in RiscFree* IDE 6.2. Processor System Debug 6.3. Heterogeneous Multicore Debug 6.4. Debugging µC/OS-II Application 6.5. Debugging FreeRTOS Application 6.6. Debugging Zephyr Application 6.7. Arm* HPS On-Chip Trace 6.8. Debugging the Arm* Linux Kernel 6.9. Debugging Target Software in an Intel® Simics Simulator Session
6.1. Debug Features in RiscFree* IDE x
6.1.1. Viewing Global Variables 6.1.2. Launching Memory Browser 6.1.3. Debugger Console 6.1.4. Specifying the SVD File 6.1.5. Breakpoint Settings 6.1.6. JTAG UART Output Terminal
6.2. Processor System Debug x
6.2.1. GUI for Debugging
6.3. Heterogeneous Multicore Debug x
6.3.1. Importing Nios® V Processor and Arm* HPS Projects 6.3.2. Setting Core Configuration
6.7. Arm* HPS On-Chip Trace x
6.7.1. Trace Bar 6.7.2. Trace View
6.8. Debugging the Arm* Linux Kernel x
6.8.1. Preparing Linux for Kernel Debugging 6.8.2. Debugging the Arm* HPS Linux Kernel
7. Debugging with Command-Line Interface x
7.1. Running Ashling* GBD Server 7.2. Running GDB 7.3. Nios® V Processor Example 7.4. ARM HPS Core Example
A. Appendix x
A.1. Optional Toolchain Configuration A.2. Performing External Tools Configuration A.3. Help Content A.4. Open-Source Components in RiscFree* IDE
A.1. Optional Toolchain Configuration x
A.1.1. Toolchain for Application and BSP A.1.2. Toolchain for Arm* Processor A.1.3. Modifying Toolchain Configuration
1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix

9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

Document Version Quartus® Prime Version Changes
2024.05.13 24.1
  • Added a note in topic Graphical User Interface.
  • Updated topic Importing Nios® V Processor Project.
  • Updated Table: Options and Description.
  • Updated Table: RiscFree* IDE Open-Source Components.
2023.12.14 23.4
  • Updated Table: RiscFree IDE Open-Source Components in Open-Source Components in RiscFree IDE.
2023.12.01 23.3 Added new topics:
  • Intel® Simics® Simulator Support.
  • Ashling* RiscFree* IDE for Intel® FPGAs Interaction with Intel® Simics® Simulator for FPGAs.
  • Debugging the Linux Kernel.
  • Debugging in Intel® Simics® .
  • Debugging with Command-Line Interface.
  • Updated Table: RiscFree IDE Open-Source Components in Open-Source Components in RiscFree IDE.
2023.07.20 23.2
  • Added a link to AN 980: Nios® V Processor Intel® Quartus® Prime Software Support in the topic Intel® Quartus® Prime Software Support.
  • Updated Table: RiscFree IDE Open-Source Components in Open-Source Components in RiscFree IDE.
2023.04.10 23.1
  • Edited topic Debug Setup for Nios V Processor System to add the mention of Zephyr and FreeRTOS.
  • Updated the following figures:
    • Debug Configurations for Nios V Processor —Debugger Tab
    • Debugger Settings for Intel Agilex® 7 Arm Cortex-A53 Core
    • List of Available Cores for the Selected Target Device in RiscFree IDE
    • Startup Tab Settings
    • Enabling OS Aware Debugging in Heterogeneous Debugging
  • Added new topics:
    • Debugging FreeRTOS Application.
    • Debugging Zephyr Application.
  • Added Ashling* RiscFree* IDE for Intel FPGAs and OpenCSD to the table RiscFree IDE Open-Source Components.
  • Updated product family name to Intel Agilex® 7.
2022.12.19 22.4
  • Added new topics in Debugging with RiscFree IDE.
    • Arm HPS On-Chip Trace
    • Trace Toolbar
    • Trace View
  • Updated Table: RiscFree IDE Open-Source Components in Open-Source Components in RiscFree IDE.
2022.10.31 22.1std
  • Added more devices to the Supported Devices section.
  • Added links to the documentations supporting Quartus® Prime Standard Edition in Supported Devices section.
  • Updated references from Intel Quartus Prime Pro Edition to Intel Quartus Prime to indicate support for both Pro and Standard Edition.
  • Added steps to download Ashling* RiscFree* IDE for Intel® FPGAs in the Standalone Installation section.
  • Added a figure Installation Warning Message in Standalone Installation with Supported Intel Quartus Prime Software section.
2022.09.26 22.3
  • Updated the document title from RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide to Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide.
  • Updated the features in the About the RiscFree* IDE section.
  • Added a note in the Standalone Installation with the Quartus® Prime Pro Edition Programmer and Tools session.
  • Updated the RiscFree* IDE launching method and added a note to avoid the niosv-stack-report warning for standalone installation in the Command Line Interface section.
  • Added information on Nios® V applications OS support in the Debug Setup for Nios® V Processor System section.
  • Update the Setting Debug Configurations and Downloading Nios® V Project Using RiscFree* IDE section.
    • Updated the Debug Configurations for Nios® V—Main Tab diagram.
    • Added step on OS Awareness settings.
  • Added note to state that RiscFree* IDE supports Arm* HPS standalone debug in the Debug Setup for Arm* Hard Processor System section.
  • Updated the Setting Core Configuration section.
    • Updated the Target Application Tab Settings diagram.
    • Added step on OS Awareness settings.
  • Added the following sections:
    • Debugging µC/OS-II Application
    • Help Content
    • Open-Source Components in RiscFree* IDE
2022.06.21 22.2 Initial release.
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