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1. About the RiscFree* IDE
2. Installation and Setup
3. Getting Started with RiscFree* IDE
4. Debug Setup for Nios® V Processor System
5. Debug Setup for Arm* Hard Processor System
6. Debugging with RiscFree* IDE
7. Debugging with Command-Line Interface
8. Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide Archives
9. Document Revision History for the Ashling RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide
A. Appendix
6.1. Debug Features in RiscFree* IDE
6.2. Processor System Debug
6.3. Heterogeneous Multicore Debug
6.4. Debugging µC/OS-II Application
6.5. Debugging FreeRTOS Application
6.6. Debugging Zephyr Application
6.7. Arm* HPS On-Chip Trace
6.8. Debugging the Arm* Linux Kernel
6.9. Debugging Target Software in an Intel® Simics Simulator Session
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6.2. Processor System Debug
This section is a generic debugging section where the debugging steps are the same for Nios® V processor and Arm* HPS debugging.
Follow the guidelines in this section to start debugging the program using GUI or the GDB console after completing the steps from the following sections:
- Setting Debug Configurations and Downloading Nios® V Processor Project Using RiscFree* IDE
- Setting Debug Configurations and Downloading Arm* HPS Project Using RiscFree* IDE