Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 5/13/2024
Document Table of Contents

6.3.2. Setting Core Configuration

To set the core configuration, follow these steps:

  1. Right click project directory (either HPS or Nios® V application) and select Debug > Debug Configurations.
  2. Select Ashling Heterogenous Multicore Debugging > cortex-a53-sum.elf.
  3. Under the Device tab, set these settings:
    • Debug probe: Agilex SI/SoC Dev Kit
    • JTAG/SWD frequency: 16 MHz
    • Transport type: JTAG
  4. Click the Auto-detect Scan Chain to list out all the available cores.
  5. Under Core Configuration, select Cortex-A53 and Nios V/m.
    Figure 18. List of Available Cores for the Selected Target Device in RiscFree* IDE
  6. Set the core specific configuration for each core under the Debugger tab.
  7. Specify the .elf file for each core under the Target Application tab. In this example, the target applications are added as nios-v-sum.elf for Nios V/m core and cortex-a53-sum.elf for Cortex-A53 core.
    Note: You can specify multiple .elf file for a single core.
    Figure 19. Target Application Tab Settings
  8. Set the breakpoint at a specific function under the Startup tab. This debug example uses the default settings.
    Figure 20. Startup Tab Settings
  9. Based on the OS you use, configure the OS Awareness settings as follows:
    • Intel® HAL: No OS Awareness configuration is required.
    • Other OS: Under the OS Awareness tab, turn on Enable OS Aware Debugging, and select the OS as listed below:
      • µC/OS and Version: II
      • FreeRTOS and Version: 10.4.1
      • Zephyr and Version: 3.1.0
    Figure 21. Enabling OS Aware Debugging in Heterogeneous Debugging
  10. Click Debug when all configuration is complete. All cores selected for debug are launched.
    Figure 22. Heterogeneous Multicore Debug View in RiscFree* IDE
  11. To debug two cores simultaneously, go to Window > Show View > Registers. Then, make a copy of the existing debug view using the Open new View icon.
    Figure 23. Register Window
  12. In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 3 Core 0 (Cortex-A53)]. Pin one copy of the debug view to Arm processor using the Pin to Debug Context icon.
    Figure 24. Arm Processor (Core 0) Register View
  13. In the Heterogenous Multicore Debug View pane, select Thread #1 [TAP 2 (Nios V/m Hart 0)]. Pin second copy of the debug view to Nios V processor using the Pin to Debug Context icon.
    Figure 25. Nios V Processor (Core 4) Register View