Ashling* RiscFree* Integrated Development Environment (IDE) for Intel® FPGAs User Guide

ID 730783
Date 5/13/2024
Document Table of Contents

6.7. Arm* HPS On-Chip Trace

You can configure and capture the Arm HPS On-Chip Trace with Intel® FPGA Download Cable II. The following table shows the Arm* trace sources that generate instruction trace:
Table 11.  Arm Trace Source
Arm Trace Source Encoding Type Description Supported Device
Program Trace Macrocell (PTM) PTM A real-time trace module providing instruction tracing of a processor
  • Arria® 10
  • Intel® Cyclone® V
Embedded Trace Macrocell (ETM) ETMv4 The Arm trace source that captures data and instruction trace
  • Agilex® 7
  • Stratix® 10
Follow the steps to enable and configure the Trace feature:
  1. Launch Ashling Arm Hardware Debugging, and click the Trace tab.
    Figure 33. Trace Tab
  2. Click the Enable trace checkbox to enable the trace selected settings. The Trace architecture defaults to Arm Coresight. The trace selected settings appear in the following tab:
    1. Capture Settings
    2. Producer Settings
    3. Trigger/Filter Settings
      Figure 34. Capture Settings Sub-Tab
  3. Under the Capture Settings tab, set this settings:
    1. Select On-chip.
    2. Select one of the following Device Buffer Configuration:
      1. Embedded Trace FIFO (ETF) — stores trace data in small and fixed size trace buffer.
      2. Embedded Trace Router (ETR) — routes the trace data to the system memory. You need to specify the RAM location and Size .
    3. Wrap-around — enables overwriting old trace data with the new trace data when the trace buffer is full.
      Note: Wrap-around is optional. If you do not select Wrap-around, trace capture stops when the trace buffer is full.
  4. Under Producer Settings tab, set this settings:
    1. Select your preferred settings:
      1. Cycle Accurate Trace — captures trace on all cycles even if there is no trace to output on that cycle.
      2. Enable context ID — enables the tracing of the ASID and the current process ID.
      3. Enable timestamp — enables timestamps in your trace.
    2. For Encoding type, you can select ETMv4 or PTM. Refer to Table Arm Trace Source for more details.
      Note: ETMv3 is an older version of ETMv4 and not supported by Intel devices.
      Figure 35. Producer Settings Sub-tab
  5. Under Trigger/Filter Settings tab, click the Enable trigger checkbox.
    Figure 36. Trigger/Filter Settings Tab
  6. Click Add to bring up the Add Trigger dialog box as shown below:
    Figure 37. Add Trigger Dialog Box
    1. For Trace action, choose one of the following options:
      1. Trace include— limits trace to the selected address range
      2. Trace exclude— excludes trace from the selected address range
      3. Trace start point— starts tracing when the selected address is executed
      4. Trace stop point— stops tracing when the selected address is executed
    2. For Core, use the same core that you select in Debugger tab.
    3. For Access type, select the only available option — Instruction execution as instruction trace and to support trigger.
  7. Once you complete the configuration, click Debug.
  8. Open Trace view via Window > Show > View > Other > Debug > Trace. Click Fetch, decode and populate trace data button on the top right of the window to fetch trace data from the target and display in the Trace view as shown below.
    Figure 38. Trace View