F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
Document Table of Contents

2. Overview of the F-Tile JESD204C Intel® FPGA IP

The F-Tile JESD204C Intel® FPGA IP is a high-speed point-to-point serial interface for digital-to-analog (DAC) or analog-to-digital (ADC) converters to transfer data to FPGA devices. This unidirectional serial interface runs at a maximum data rate of 32.44032 Gbps. This protocol offers higher bandwidth, low I/O count and supports scalability in both number of lanes and data rates.

The F-Tile JESD204C Intel® FPGA IP addresses multidevice synchronization using Subclass 1 to achieve deterministic latency.

The F-Tile JESD204C Intel® FPGA IP supports true simplex, TX-only, RX-only, and Duplex (TX and RX) mode. The Intel® FPGA IP is a unidirectional protocol where interfacing to ADC utilizes the transceiver RX path and interfacing to DAC utilizes the transceiver TX path.

The F-Tile JESD204C TX and RX cores run on a link clock with 64-bit data width, which reduces the area utilization.

The Intel® FPGA IP incorporates:

  • Media access control (MAC)—data link layer (DLL) and transport layer (TL) blocks that control the link states.
  • Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.

The transport layer (TL) in the MAC controls the assembling and disassembling of the frames.

Figure 1.  F-Tile JESD204C Duplex Functional Block Diagram
Figure 2.  F-Tile JESD204C TX-only Functional Block Diagram
Figure 3.  F-Tile JESD204C RX-only Functional Block Diagram