F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
Document Table of Contents

5.5.1. Interrupt Configuration for TX and RX

When configuring the control and status registers, you must determine which error types to promote as interrupts and which ones to disable.

To determine the error types as interrupts or otherwise, configure the F-Tile JESD204C TX Error Enable and RX Error Enable registers at offset 0x64.

By default, the IP promotes all errors as interrupt enable except the ECC correctable error for the RX. The following examples depict errors that you can exclude as interrupts:

  • The F-Tile JESD204C TX core detects data bubble in the Avalon® streaming interface. If your system design has no data bubble, and there is a continuous data stream from the upstream device, you can disable interrupt for this error type.
  • If your system design do not keep track of correctable error (CE) occurrences, you may disable the intruder.
    Note: You may want to enable CE interrupt for high-end server systems, to keep track of the CE events as a predictor for future events. Predicting future events enables the IP to execute some form of preventive maintenance or part placement to prevent the likelihood of dreaded uncorrectable errors and system panics.