F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
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5.4. SYSREF Sampling

You can choose to enable continuous SYSREF sampling or a single SYSREF detection.

The software logic programs the clock cleaner to the SPI to enable SYSREF generation. To resample SYSREF , the software logic writes to the SYSREF_CTRL registers to enable either a continuous sampling or a single detection. If both bits are enabled, continuous sampling takes precedence.

You may want to disable SYSREF sampling after some time. Disabling SYSREF sampling also disables the continuous sampling mode, and subsequently programs the clock cleaner to disable SYSREF output.

Consider one of the following recommendations to configure the SYSREF resampling flow:

  1. Set the sysref_singledet, sysref_alwayson, and sysref_lemc_err_en_reinit register bits to 1.
    • If a new SYSREF edge is detected, the F-Tile JESD204C IP clears the sysref_singledet bit and automatically starts a link reinitialization.
    • All the Avalon® streaming interface signals return to default state.
    • The LEMC block resets to reflect the newly detected SYSREF edge.
    • All the Avalon® streaming interface signals are active again based on a new LEMC data.
    • If LEMC error interrupt is enabled, the F-Tile JESD204C needs to service and clear the error.
  2. Set the sysref_singledet bit to 1 and sysref_alwayson bit to 0.
    • If a new SYSREF edge is detected, the F-Tile JESD204C IP clears the sysref_singledet bit, but no automatic start of link reinitialization.
    • All the Avalon® streaming interface signals remain active.
    • The LEMC block resets to reflect the newly detected SYSREF edge.
      • In the TX IP, the egress sync header (SH) adjusts as LEMC undergoes realignment to the new SYSREF edge. The corresponding RX (that receives the adjusted SH) may subject to SH-related errors.
      • In the RX IP, the ingress Avalon® streaming data does not get affected because the change of LEMC does not impact the already streaming data. However, the link loses its deterministic latency characteristic. To restore the deterministic latency behavior, a link reinitialization is required.
    • You must set the link_reinit bit to 1 after sysref_singledet clears to start a link reinitialization.
    • All the Avalon® streaming interface signals return to default state, and get reactivated based on a new LEMC data.
To better handle potential race conditions between the assertion of the link_reinit bit (through user-specified or auto reinitialization) and the assertion of the sysref_singledet bit, the IP imposes the following behavior:
  • For TX core: If the the link_reinit bit asserts), the Avalon® streaming interface deactivates. After the link reinitialization is complete, the Avalon® streaming interface gets activated only when the sysref_singledet deasserts.
  • For RX core: If the the link_reinit bit asserts, the Avalon® streaming interface deactivates. After the link reinitialization is complete, the Avalon® streaming interface gets activated only when the sysref_singledet deasserts, and SH (j204c_rx_sh_lock) and EMB (j204c_rx_emb_lock) have achieved lock.