F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
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3.1. Clocks

The F-Tile JESD204C IP runs on link clock (link layer) and frame clock (transport layer). The transceiver runs in the link clock domain and the serial clock domain.

Table 10.   F-Tile JESD204C IP Clocks
Clock Signal Formula Description

TX/RX device clock


PLL selection The PLL reference clock used by the TX Transceiver PLL or RX CDR. This is also the recommended reference clock to the Core PLL.

TX/RX link clock



Line rate/66 The timing reference for the F-Tile JESD204C IP. The link clock is line rate divided by 66 because the link clock operates in a 66-bit data bus domain architecture after 64B/66B encoding.

TX/RX frame clock



(Link clock frequency*FCLK_MULP) MHz The frame clock as per the JESD204C specification. The frame clock is always 1x or 2x of the link clock.

TX/RX Avalon® memory-mapped clock



The configuration clock for the F-Tile JESD204C IP control and status registers through the Avalon® memory-mapped interface. This clock is asynchronous to all the other clocks. The frequency range of this clock is 75 to 125 MHz.

TX PHY clock


Line rate/64

The PHY clock internally generated from the transceiver parallel clock for the TX path.

Transceiver reconfiguration clock


The transceiver reconfiguration clock. The frequency range of this clock is 100 MHz.
System PLL clock


System PLL clock frequency >= Native clock frequency The F-Tile system PLL clock frequency is user-defined. The system PLL clock frequency is greater or equal to the native clock frequency.