F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Document Table of Contents

4.7. Compiling the F-Tile JESD204C IP Design

Refer to the Designing with the F-Tile JESD204C Intel FPGA IP before compiling the F-Tile JESD204C IP core design.

To compile your design, click Start Compilation on the Processing menu in the Intel® Quartus® Prime software. You can use the generated .ip or .qip file to include relevant files into your project.