F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Document Table of Contents
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5.7.1. RBD Tuning Mechanism

The following figures focus on the RBD tuning mechanism and how RBD count and RBD offset are used to tune the deterministic latency.

Figure 14. RBD Tuning
Figure 15. RBD Tuning (Power Cycle Variation)
Figure 16. RBD Tuning (Utilizing RBD Offset for Early Release)
Figure 17. RBD Tuning (LEMC Slip)
Figure 18. RBD Tuning (LEMC Slip, if RBD Tuning Using RBD Offset is Not Used)
Figure 19. RBD Tuning (RBD Offset Tuning Legal Range)
Figure 20. RBD Tuning (RBD Tuning when RBD Count Arrival Shifts Before and After LEMC in Multi-Reset)
Figure 21. RBD Tuning (RBD Offset Tuning - Legal Range)
Figure 22. RBD Tuning (RBD Offset Tuning using RBD Offset - Legal Range)

The following figure shows the RBD tuning in actual numerical representative used in the F-Tile JESD204C RX IP core.

Figure 23. RBD Tuning (RBD Offset using Numerical Representative for LEMC = 15 Down to 0)