F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
Document Table of Contents

10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2024.01.26 23.3 2.2.0
  • Updated Table: F-Tile JESD204C IP Clocks
    • Updated description for TX/RX device clock.
  • Added figures to the Device Clock section:
    • JESD204C Subsystem with Shared Transceiver Reference Clock and Core Clock
    • JESD204C Subsystem with Separate Transceiver Reference Clock and Core Clock
2023.11.15 23.3 2.2.0
  • Updated Table: RX Interrupt Handler Recommendations
    • Updated the ISR Handler Operation for rx_gb_underflow_err and rx_gb_overflow_err.
  • Updated Scrambler/Descrambler topic.
  • Updated F-Tile JESD204C Intel FPGA IP Features topic to add Riviera-PRO* simulator support.
2023.06.26 23.2 2.1.0
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Release Information
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters
    • Added Multilink mode parameter
  • Updated Table: Top-level Receiver IP Core Signals
    • Added information about the following two new signals for Multilink mode:
      • j204c_rx_dev_emblock_align
      • j204c_rx_alldev_emblock_align
2023.04.11 23.1 2.0.2
  • Updated Table: Brief Information about the F-Tile JESD204C Intel® FPGA IP
    • Updated description for Core Features
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance.
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Updated value for Data rate parameter
  • Replaced individual Transmitter Registers and Receiver Registers sections with a new combined Transmitter and Receiver Registers section that provides links to register maps
  • Removed Table: Related Documents
  • Updated the product family name to "Intel Agilex

    7"

2023.02.10 22.2 1.1.0
  • Fixed the links in Table 1: Related Documents.
2022.08.18 22.2 1.1.0
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance
2022.06.21 22.2 1.1.0
  • Updated Table: F-Tile JESD204C IP Clocks
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Updated value and description for Transceiver type parameter
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Performance:
    • Updated Maximum Data Rate (Gbps) column
  • Updated Table: Top-level Transmitter IP Core Signals
    • Added j204c_syspll_div2_clk port signal
  • Updated Table: Top-level Receiver IP Core Signals
    • Added j204c_syspll_div2_clk port signal
  • Updated topic: F-Tile JESD204C Intel FPGA IP User Guide Archives
2022.04.26 21.4 1.0.0
  • Added Figure: Example Timing Diagram of j204c_txfclk_ctrl when FCLK_MULP=2
  • Updated Table: Top-level Transmitter IP Core Signals
  • Updated Table: Top-level Receiver IP Core Signals
2021.12.13 21.4 1.0.0
  • Added new topics:
    • Multi-Device Synchronization
    • Multi-Device DAC Application for Subclass 1
    • Multi-Device ADC Application for Subclass 1
    • RBD Tuning Mechanism
    • Transceiver Toolkit
  • Added NPDME to Table: Acronym List.
  • Updated Table: Related Documents.
  • Updated Table: F-Tile JESD204C Intel® FPGA IP Parameters:
    • Added a new parameter—Enable debug endpoint for PMA Avalon® memory-mapped interface .
    • Updated parameter name Enable dynamic reconfiguration to Enable PMA Avalon® memory-mapped interface .
  • Updated the following figures:
    • Figure: F-Tile JESD204C Duplex Functional Block Diagram
    • Figure: F-Tile JESD204C RX-only Functional Block Diagram
  • Updated the descriptions and figure in F-Tile JESD204C TX Reset Sequence.
  • Updated the descriptions and figure in F-Tile JESD204C RX Reset Sequence.
  • Updated the description for reconfig_xcvr_clk in Table: Top-level Transmitter IP Core Signals.
  • Added information about reconfig_xcvr_reset in the following tables:
    • Table: Top-level Transmitter IP Core Signals
    • Table: Top-level Receiver IP Core Signals
  • Removed xcvr_pll_locked from Table: Top-level Transmitter IP Core Signals.
  • Updated Deterministic Latency to correct the legal value of RBD count.
  • Corrected the description for F-Tile JESD204C MAC to and from the PHY interface in Table: F-Tile JESD204C Intel® FPGA IP Interfaces to clarity that the IP can generate MAC and PHY configuration.
2021.10.11 21.3 1.0.0 Initial release.