F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
Document Table of Contents

3.1.1. Device Clock

In a converter device, the sampling clock is typically the device clock. The F-Tile JESD204C IP uses the device clock to generate the desired internal clocks for the transceivers and core logic.

For the F-Tile JESD204C IP link in an FPGA logic device, you can select one of the options provided in the PLL/CDR reference clock frequency parameter in the F-Tile JESD204C IP parameter editor.

In the single reference clock design, both sets of pins are driven by the same clock source. The device clock is used as the transceiver PLL reference clock and also the core PLL reference clock. In the dual reference clock design, each set of pins are driven by a different clock source. The device clock is used as the core PLL reference clock and the other reference clock (phase-locked to device clock) is used as the transceiver PLL reference clock. If you want to use the same reference clock for the transceiver and core PLLs, you must use two separate input pins for these PLL reference clocks in your design. Use a common clock source on the board to generate two separate clocks of the same frequency to drive the inputs.

The device clock frequency depends on the data rate and total number of lanes. When you generate the IP, the Intel® Quartus® Prime Pro Edition software provides the available reference frequency for the transceiver PLL and core PLL based on your selection.

For Subclass 1 application, ensure that the routing of the SYSREF signal and the device clock to the FPGA's core logic has matching trace lengths.

Figure 4. JESD204C Subsystem with Shared Transceiver Reference Clock and Core Clock
Figure 5. JESD204C Subsystem with Separate Transceiver Reference Clock and Core Clock