F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
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3.2.1. LEMC Counter

F-Tile JESD204C IP maintains an LEMC counter that counts from 0 to (E*32)–1 and wraps around again.

In Subclass 0 system, the LEMC counter starts at the deassertion of the link reset signal, without waiting for SYSREF detection.

In Subclass 1 deterministic latency system, all transmitters and receivers receive a common SYSREF, and the LEMC counter resets within two link clock cycles. SYSREF must be the same for the converter devices, which are grouped and required to be synchronized together.

Maximum SYSREF frequency = data rate/(66x32xE).

Table 11.  Example of SYSREF Frequency CalculationIn this example, you can choose to perform one of the following options:
  • Provide two SYSREF and a device clock; in which the ADC groups share the device clock and the two SYSREF clock (1.42 MHz and 2.84 MHz).
  • Provide 1 SYSREF running at 1.4 MHz and a device clock for the two ADC groups and one DAC group because the SYSREF period in the DAC is in the multiplication of n integer.
Group Configuration SYSREF Frequency
ADC Group 1 (2 ADCs)
  • LMF = 222
  • E = 2
  • Data rate = 6,000 Mbps
(6,000 MHz/(66x32x2) = 1.42 MHz
ADC Group 2 (2 ADCs)
  • LMF = 811
  • E = 1
  • Data rate = 6,000 Mbps
(6,000 MHz/(66x32x1) = 2.84 MHz
DAC Group 3 (2 DACs)
  • LMF = 222
  • E = 1
  • Data rate = 3,000 Mbps
(3,000 MHz/(66x32x1) = 1.42 MHz
Note: 1.42 MHz is the common maximum SYSREF frequency. You can lower the frequency to 0.71 MHz and the design still works.