F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
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3.1.2. Frame Clock and Link Clock

The frame clock frequency always equals the link clock frequency times the frame clock frequency multiplier (FCLK_MULP):

Frame clock frequency = FCLK_MULP x Link clock frequency

You can set the frame clock frequency multiplier through the F-Tile JESD204C IP parameter editor. The valid values for the multiplier are limited to 1 and 2. Because of the fixed relationship between the link clock and the frame clock, the Avalon® streaming data does not constantly stream.

To provide consistency across the design regardless of frame clock and sampling clock, the link clock is used as a timing reference.

The IOPLL core should provide both the frame clock and link clock from the same PLL as these two clocks are treated as synchronous in the design.

For JESD204C TX and RX IPs, j204c_txlclk_ctrl or j204c_rxlclk_ctrl provides the phase information of a link clock rising edge that aligned to a frame clock rising edge.

Similarly, j204c_txfclk_ctrl or j204c_rxfclk_ctrl provides the phase information of a frame clock rising edge that aligned to a link clock rising edge. This additional clock phase information handles the transfer between frame clock and link clock in a synchronous manner.

Figure 6. Example Timing Diagram of j204c_txfclk_ctrl when FCLK_MULP=2