F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
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8. Control and Status Registers

The control and status registers refer to byte addressing as seen by the software, and as implemented by hardware. All registers that are Read-Writable must be protected to comply with Security Development Lifecycle (SDL) practices. You are required to perform the register access protection.
Table 21.  Register Access Type and DefinitionThis table describes the register access type for Intel® FPGA IPs.
Access Type Definition
RO Software read-only (no effect on write). The value is hard-tied internally to either '0' or '1' and does not vary.
RO/V Software read-only (no effect on write). The value may vary.
RC
  • Software reads and returns the current bit value, then the bit self-clears to 0.
  • Software read also causes the bit value to be cleared to 0.
RW
  • Software reads and returns the current bit value.
  • Software writes and sets the bit to the desired value.
RW1C
  • Software reads and returns the current bit value.
  • Software writes 0 and has no effect.
  • Software writes 1 and clears the bit to 0 if the bit has been set to 1 by hardware.
  • Hardware sets the bit to 1.
  • Software clear has higher priority than hardware set.
RW1S
  • Software reads and returns the current bit value.
  • Software writes 0 and has no effect.
  • Software writes 1 and sets the bit to 1.
  • Hardware clears the bit to 0 if the bit has been set to 1 by software.
  • Software set has higher priority than hardware clear.