F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
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7. Interface Signals

The F-Tile JESD204C Intel® FPGA IP uses the signals from the following interfaces.

Table 18.   F-Tile JESD204C Intel® FPGA IP Interfaces
Interface Description
F-Tile JESD204C MAC to and from the PHY interface The IP allows you to generate MAC and PHY configuration.
Avalon® memory-mapped interface
  • The IP uses the Avalon® memory-mapped interface for reading and writing on the F-Tile JESD204C IP slave component in a memory-mapped system.
  • The Avalon® memory-mapped slave interface allows upstream devices to access internal control and status registers.
  • The Avalon® memory-mapped slave is referred to as Management interface.
  • The Avalon® memory-mapped slave interface is designed as an asynchronous domain to the F-Tile JESD204C Link clock and Frame clock domains.
  • If you want to keep the Avalon® memory-mapped slave interface as a synchronous domain to the F-Tile JESD204C Link clock domain, you may do so provided that the domain is within the minimum and maximum frequency specified for j204_tx_avs_clk or j204_rx_avs_clk.
Avalon® streaming interface
  • The IP uses the following types of Avalon® streaming interface signals:
    • Avalon® streaming data interface, which operates in txframe_clk and rxframe_clk domains.
    • Avalon® streaming control sample interface, which operates in txframe_clk and rxframe_clk domains.
    • Avalon® streaming command interface, which operates in txlink_clk and rxlink_clk domains.
Note: You should terminate any unused signals.