F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 1/26/2024
Public
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4.6. Parameterizing and Generating the IP

Refer to F-Tile JESD204C Intel FPGA IP Parameters for the IP parameter values and description.

  1. In the IP Catalog (Tools > IP Catalog), locate and double-click the F-Tile JESD204C Intel® FPGA IP.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP variation files in your project. If prompted, also specify the target Intel® FPGA device family and output file HDL preference. Click OK.
  3. After parameterizing the core, go to the Example Design tab and click Generate Example Design to create the simulation testbench. Skip to step 5 if you do not want to generate the design example.
  4. Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.
    The testbench and scripts are located in the <example_design_directory>/simulation folder.

    The Generate Example Design option generates supporting files for the following entities:

    • IP core design example for simulation—refer to Generating and Simulating the Design Example section in the respective design example user guides.
    • IP core design example for synthesis—refer to Compiling the F-Tile JESD204C Design Example section in the respective design example user guides.
  5. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis and simulation.

    The top-level IP variation is added to the current Intel® Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Note: Some parameter options are grayed out if they are not supported in a selected configuration or it is a derived parameter.