F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 5/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler 3.5. Data Mapping Operation
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

2.4. Performance and Resource Utilization

Table 7.   F-Tile JESD204C Intel® FPGA IP Performance
Device Family PMA Speed Grade Core Speed Grade Maximum Data Rate (Gbps)
FCLK_MULP = 1 FCLK_MULP = 2

Agilex™ 7 (F-Tile)

Agilex™ 9 (F-Tile)

1 –1 32.44032 18.15
–2 32.44032 18.15
2 –1 28.89481 18.15
–2 28.89481 18.15
–3 24.33024 18.15
3 –3 17.4 16

The following table lists the estimated resource utilization data of the F-Tile JESD204C IP. These results are obtained using the Quartus® Prime software targeting the Agilex™ 7 AGIA027R29A1E2VR0 device.

The variations for resource utilization are configured with the following parameter settings:

Table 8.  Parameter Settings to Obtain the Resource Utilization Data
Parameter Setting
JESD204C Wrapper Both Base and PHY
JESD204C Subclass 1
Data Rate 17.4 Gbps
Bonding Mode Non-bonded
Reference Clock Frequency 174.0 MHz
Enable Scrambler (SCR) On
Enable Error Code Correction (ECC_EN) Off
Table 9.   F-Tile JESD204C IP Resource Utilization for Agilex™ 7 Devices
Variants L M F FCLK_MULP WIDTH_MULP ALM ALUT Logic Register M20K
TX 4 8 6 1 4 2709.2 3144 4199 8
4 8 6 2 2 3230.1 3527 5096 8
4 8 4 1 2 2524.8 2938 3824 8
4 8 4 2 1 3336.6 3700 5374 8
2 8 6 1 4 1566.6 1787 2372 4
2 8 6 2 2 1876.8 2023 2856 4
8 8 3 1 8 5327.4 6116 8667 16
8 8 3 2 4 6539.9 7062 10609 16
3 8 4 1 2 1957.2 2253 2970 6
3 8 4 2 1 2316.7 2558 3590 6
16 4 8 1 1 8858.5 10159 13857 32
16 4 8 2 1 9301.0 10559 14777 32
RX 2 8 12 1 2 2211.1 2793 2956 12
2 8 12 2 1 2178.9 2735 2859 12
1 2 8 1 1 1091.9 1375 1328 5
1 2 8 2 1 1097.5 1379 1332 5
1 4 24 1 1 1222.8 1517 1643 6
1 4 24 2 1 1223.6 1515 1644 6
8 1 1 1 8 6117.3 7617 6899 30
8 1 1 2 4 6086.5 7681 7185 30
3 2 4 1 2 2577.5 3249 3047 12
3 2 4 2 1 2680.4 3444 3336 15
16 4 8 1 1 11363.0 14200 12802 51
16 4 8 2 1 11445.9 14213 12823 51
1 Maximum data rate is reduced to 27.2 Gbps with ECC enabled.
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