1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Intel FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. F-Tile JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the F-Tile JESD204C IP Design
4.8. Programming an FPGA Device
5.8. Transceiver Toolkit
The F-Tile JESD204C Intel® FPGA IP supports the transceiver toolkit to access the PMA channels of the IP to perform tuning, eye capture, BER tests, and others.
The Quartus® Prime transceiver toolkit accesses the PMA through the PMA Avalon® memory-mapped interface.
You have the option to turn on Enable debug endpoint for PMA Avalon memory-mapped interface to enable the NPDME in the parameter editor of the F-Tile JESD204C Intel® FPGA IP. When you turn on this option, the IP instantiates an NPDME module internally. This option is available only when the PMA Avalon® memory-mapped interface is enabled.