F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 5/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler 3.5. Data Mapping Operation
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

3.5. Data Mapping Operation

The following examples show the visualization of the data mapping operation in F-Tile JESD204C IP towards serialization.
Figure 7. Transmitter Data Mapping for LMF 2812

Pre-requisite:

For the transmitter direction, once the j204c_tx_avst_ready signal is asserted, the transport layer begins accepting data from the j204c_tx_avst_data bus for data mapping. This process, known as the USER_DATA phase indicates that the F-Tile JESD204C TX IP core is operational.

On the receiver side, the assertion of j204c_rx_avst_valid marks the start of the F-Tile JESD204C RX IP core operation and USER_DATA phase.

Once the USER_DATA phase has started, it cannot be backpressured regardless of the j204c_tx_avst_ready/j204c_rx_avst_valid status. Data mapping operation in the transport layer is synchronous to j204c_txframe_clk/j204c_rxframe_clk.

Table 12.  Transmitter Data Mapping Details for LMF 2812
Layer/Module Description Phase Description
Transport Layer Data is assembled into octets and framed per F value chosen by the user. 1 8 converters are divided into 2 lanes with 4 converters each.
2 One sample is collected from the converter (S = 1) with a size of 24-bits (N = 24).
3 Since N’ is also set to 24, no tail bit will be added to the Nibble group.
4 Nibble group is assembled into octets. Octets are then arranged into frames of user-selected F size, which in this case is 12. A 24-bit sample from converters produces 3 octets.
5 Since the width multiplier (WIDTH_MULP) is set to 2, two sets of data samples of size 192 bits are needed to satisfy the Avalon® streaming interface data bus size of 384 bits (avst_data bus width = M*S*N*WIDTH_MULP = 8*1*24*2 = 384 bits). As the two sets of frames per each lane is ready, user data is sent to the Link Layer.
Link Layer Data scrambling/descrambling and SH (Sync Header) encoding/decoding. 6 The transmitter scrambles the user data from the transport layer for a proper balance of ones and zeros over the physical link. Per the JEDEC standard, scrambling is required for all encoding modes and is disabled for normal operation.
7 SH of size 2-bits is encoded into the 8 octets which make up 64-bits of data to form a 66-bit block. For the F-Tile JESD204C IP, CRC-12 encoding/decoding is supported.
8 The structure of which user data is arranged prior to being sent to the PMA is through a block structure, which is a container consisting of a 2-bit unscrambled SH followed in time by 8 octets of scrambled user data.
9 32 blocks are arranged together and is called a multiblock.
10 The E number of the multiblock are then combined to form an extended multiblock (EMB). The E value must be set to a value where the frame boundaries are aligned with the E number of the multiblock. E.g. in this case, the frame boundaries are aligned with the third multiblock boundaries, so E = 3.
Gearbox Module Ensures that the data flow from the wider bus (link layer) is transmitted properly through a narrower bus (PHY layer). 11 The 66-bit width from the link layer does not directly fit the 64-bit PMA widths. The gearbox takes two 66-bit encoded words, concatenate them, and sends 128 bits (2 x 66-bit data = 132 bits, but some bits are either skipped or restructured to fit the PMA width).
Custom Cadence Module Ensure no PMA interface FIFO overflow. 12 Since the F-Tile JESD204C uses system PLL clocking mode, the custom cadence block is added to ensure TX PMA interface FIFO does not overflow due to the over clocking of the data path when using system PLL clocking mode. The Custom Cadence block is not applicable to RX direction.
Physical Layer Transmit/receive data over high-speed serial links. 13 The PHY layer converts parallel data from the link layer into serial data streams for transmission (serialization).
The following figures show examples of transmitter and receiver data mapping for LMF 444:
Figure 8. Transmitter Data Mapping for LMF 444
Figure 9. Receiver Data Mapping for LMF 444
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