Visible to Intel only — GUID: yow1630470923244
Ixiasoft
Visible to Intel only — GUID: yow1630470923244
Ixiasoft
5.1. Reset Initialization
Reset Signal | Clock Domain | Description |
---|---|---|
j204c_tx_rst_n j204c_rx_rst_n |
Asynchronous | Assertion of these signals resets all logic in the IP (MAC, TL, FIFOs). |
j204c_tx_avs_rst_n j204c_rx_avs_rst_n |
TX/RX Avalon® memory-mapped reset for CSR (j204c_tx_avs_clk/j204c_rx_avs_clk) |
|
j204c_tx_rst_ack_n j204c_rx_rst_ack_n |
Asynchronous | These signals acknowledge the state of j204c_tx_rst_n and j204c_rx_rst_n. The reset sequence completion is indicated by the assertion of these signals. |
reconfig_xcvr_reset | Asynchronous | Transceiver reconfiguration clock. Active high signal. During duplex mode, both TX and RX share the same reconfiguration pins. Intel recommends that you tie this signal to tx_avs_rst_n. |