F-Tile JESD204C Intel® FPGA IP User Guide

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ID 691272
Date 5/15/2025
Public
Document Table of Contents
Document Table of Contents x
1. About the F-Tile JESD204C Intel® FPGA IP User Guide 2. Overview of the F-Tile JESD204C Intel® FPGA IP 3. Functional Description 4. Getting Started 5. Designing with the F-Tile JESD204C Intel® FPGA IP 6. F-Tile JESD204C Intel® FPGA IP Parameters 7. Interface Signals 8. Control and Status Registers 9. F-Tile JESD204C Intel® FPGA IP User Guide Archives 10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. F-Tile JESD204C Intel® FPGA IP Features 2.4. Performance and Resource Utilization
3. Functional Description x
3.1. Clocks 3.2. Local Extended Multiblock Clock 3.3. CRC Encoding/Decoding 3.4. Scrambler/Descrambler 3.5. Data Mapping Operation
3.1. Clocks x
3.1.1. Device Clock 3.1.2. Frame Clock and Link Clock 3.1.3. System PLL
3.2. Local Extended Multiblock Clock x
3.2.1. LEMC Counter
4. Getting Started x
4.1. Installing and Licensing Intel® FPGA IP Cores 4.2. Intel FPGA IP Evaluation Mode 4.3. IP Catalog and Parameter Editor 4.4. F-Tile JESD204C IP Component Files 4.5. Creating a New Quartus® Prime Project 4.6. Parameterizing and Generating the IP 4.7. Compiling the F-Tile JESD204C IP Design 4.8. Programming an FPGA Device
5. Designing with the F-Tile JESD204C Intel® FPGA IP x
5.1. Reset Initialization 5.2. Configuration Phase 5.3. Link Reinitialization 5.4. SYSREF Sampling 5.5. Interrupt and Error Handling 5.6. Multi-Device Synchronization 5.7. Deterministic Latency 5.8. Transceiver Toolkit
5.1. Reset Initialization x
5.1.1. F-Tile JESD204C TX Reset Sequence 5.1.2. F-Tile JESD204C RX Reset Sequence
5.5. Interrupt and Error Handling x
5.5.1. Interrupt Configuration for TX and RX 5.5.2. Interrupt Top Half ISR Handler 5.5.3. Interrupt Bottom Half ISR Handler
5.6. Multi-Device Synchronization x
5.6.1. Multi-Device DAC Application for Subclass 1 5.6.2. Multi-Device ADC Application for Subclass 1
5.7. Deterministic Latency x
5.7.1. RBD Tuning Mechanism
7. Interface Signals x
7.1. Transmitter Signals 7.2. Receiver Signals
8. Control and Status Registers x
8.1. Transmitter and Receiver Registers
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide

3.2.1. LEMC Counter

F-Tile JESD204C IP maintains an LEMC counter that counts from 0 to (E*32)–1 and wraps around again.

In Subclass 0 system, the LEMC counter starts at the deassertion of the link reset signal, without waiting for SYSREF detection.

In Subclass 1 deterministic latency system, all transmitters and receivers receive a common SYSREF, and the LEMC counter resets within two link clock cycles. SYSREF must be the same for the converter devices, which are grouped and required to be synchronized together.

Maximum SYSREF frequency = data rate/(66x32xE).

Table 11.  Example of SYSREF Frequency CalculationIn this example, you can choose to perform one of the following options:
  • Provide two SYSREF and a device clock; in which the ADC groups share the device clock and the two SYSREF clock (1.42 MHz and 2.84 MHz).
  • Provide 1 SYSREF running at 1.4 MHz and a device clock for the two ADC groups and one DAC group because the SYSREF period in the DAC is in the multiplication of n integer.
Group Configuration SYSREF Frequency
ADC Group 1 (2 ADCs)
  • LMF = 222
  • E = 2
  • Data rate = 6,000 Mbps
(6,000 MHz/(66x32x2) = 1.42 MHz
ADC Group 2 (2 ADCs)
  • LMF = 811
  • E = 1
  • Data rate = 6,000 Mbps
(6,000 MHz/(66x32x1) = 2.84 MHz
DAC Group 3 (2 DACs)
  • LMF = 222
  • E = 1
  • Data rate = 3,000 Mbps
(3,000 MHz/(66x32x1) = 1.42 MHz
Note: 1.42 MHz is the common maximum SYSREF frequency. You can lower the frequency to 0.71 MHz and the design still works.
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