Visible to Intel only — GUID: rjh1637075614863
Ixiasoft
1. About the F-Tile JESD204C Intel® FPGA IP User Guide
2. Overview of the F-Tile JESD204C Intel® FPGA IP
3. Functional Description
4. Getting Started
5. Designing with the F-Tile JESD204C Intel® FPGA IP
6. F-Tile JESD204C Intel® FPGA IP Parameters
7. Interface Signals
8. Control and Status Registers
9. F-Tile JESD204C Intel® FPGA IP User Guide Archives
10. Document Revision History for the F-Tile JESD204C Intel® FPGA IP User Guide
4.1. Installing and Licensing Intel® FPGA IP Cores
4.2. Intel FPGA IP Evaluation Mode
4.3. IP Catalog and Parameter Editor
4.4. F-Tile JESD204C IP Component Files
4.5. Creating a New Quartus® Prime Project
4.6. Parameterizing and Generating the IP
4.7. Compiling the F-Tile JESD204C IP Design
4.8. Programming an FPGA Device
Visible to Intel only — GUID: rjh1637075614863
Ixiasoft
5.6.2. Multi-Device ADC Application for Subclass 1
Similar to Subclass 1 DAC scheme, the SYSREF is the reference timing that starts the LEMC counters in both converter devices and logic device (FPGA).
In this mode, the RX IP is required to synchronize the following two events of the RX IPs:
- EMB Locked
- Lane Deskew Completed
By having each RX IP synchronizing to these two events, all RX IP data can align, and hence achieve the desired synchronization behavior while meeting its deterministic nature against SYSREF.
Figure 15. Multi-Device ADC Synchronization
To enable the alldev_emblock_align and alldev_lane_align signals, select the Multilink Mode option in the JESD204C Configuration tab. This option becomes available when the Receiver or Duplex data path is selected in the IP Main tab.
In the top-level file, logically AND all RX IPs’ dev_lane_align signals to generate alldev_lane_align, and similarly, AND all dev_emblock_align signals to produce alldev_emblock_align. For example:
assign j204c_rx_alldev_lane_align = &j204c_rx_dev_lane_align; assign j204c_rx_alldev_emblock_align = &j204c_rx_dev_emblock_align;