F-Tile JESD204C Intel® FPGA IP User Guide

ID 691272
Date 5/15/2025
Public
Document Table of Contents

5.6.2. Multi-Device ADC Application for Subclass 1

Similar to Subclass 1 DAC scheme, the SYSREF is the reference timing that starts the LEMC counters in both converter devices and logic device (FPGA).
In this mode, the RX IP is required to synchronize the following two events of the RX IPs:
  1. EMB Locked
  2. Lane Deskew Completed
By having each RX IP synchronizing to these two events, all RX IP data can align, and hence achieve the desired synchronization behavior while meeting its deterministic nature against SYSREF.
Figure 15. Multi-Device ADC Synchronization

To enable the alldev_emblock_align and alldev_lane_align signals, select the Multilink Mode option in the JESD204C Configuration tab. This option becomes available when the Receiver or Duplex data path is selected in the IP Main tab.

In the top-level file, logically AND all RX IPs’ dev_lane_align signals to generate alldev_lane_align, and similarly, AND all dev_emblock_align signals to produce alldev_emblock_align. For example:
assign j204c_rx_alldev_lane_align = &j204c_rx_dev_lane_align;
assign j204c_rx_alldev_emblock_align = &j204c_rx_dev_emblock_align;