RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations

You must add a Transceiver PHY Reset Controller IP core to your design, and connect it to the RapidIO IP core reset signals. This block implements a reset sequence that resets the device transceivers correctly.

In the Transceiver PHY Reset Controller parameter editor, you must perform the following for compatibility with the RapidIO IP core:
  • Leave unchecked the Use separate RX reset per channel option.

When you generate a RapidIO IP core that target Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the Intel® Quartus® Prime software generates the HDL code for the Transceiver PHY Reset Controller in the following file: <your_ip>/altera_rapidio_<version>/synth/<your_ip>_altera_rapidio_<version>_<random_string>.v/.vhd 17

17 For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, please refer to <your_ip>_generation.rpt file to get the filename for Transceiver PHY Reset Controller HDL code, listed in the line: PHY_Reset_Controller_wrapper_name: <PHY Reset Controller name>