RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

3.1.4. Transceiver Settings

Transceiver Settings options comprise the following configuration options:

Enable transceiver dynamic reconfiguration

Enable transceiver dynamic reconfiguration parameter allows you to specify whether or not the Intel® Arria® 10 or Intel® Cyclone® 10 GX Native PHY IP core dynamic reconfiguration interface is available in the visible signals of the RapidIO IP core. If you do not expect to use this interface, you can turn off this parameter to lower the number of IP core signals to route.

Note: This parameter is available only in IP core variations that target Intel® Arria® 10 and Intel® Cyclone® 10 GX devices.
All the parameters listed below are only available when you turn on the Enable transceiver dynamic reconfiguration parameter.
  • Enable transceiver capability registers
  • Set user-defined IP identifier
  • Enable transceiver control and status register
  • Enable transceiver PRBS soft accumulators