RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

4.2.2.2. Reset Controller

All RapidIO IP core variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX include a dedicated reset control module to handle the specific requirements of the internal transceiver module. Intel® Arria® 10 and Intel® Cyclone® 10 GX RapidIO IP core variations do not include a reset controller.

The reset control module is named riophy_reset. This riophy_reset module is defined in the riophy_reset.v clear-text Verilog HDL source file, and is instantiated inside the top-level module found in the clear text < variation name >_riophy_xcvr.v Verilog HDL source file.

The riophy_reset module controls all of the RapidIO IP core's internal reset signals. In particular, it generates the recommended reset sequence for the transceiver. The reset sequence and requirements vary among device families. For details, refer to the relevant device handbook.