Product Discontinuance Notification
1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
2.2. Generating IP Cores
You can quickly configure a custom IP variation in the parameter editor.
Use the following steps to specify RapidIO IP core options and parameters in the Intel® Quartus® Prime software parameter editor:
IP Parameter Editor
- In the Intel® Quartus® Prime Pro Edition software, click File > New Project Wizard to create a new Intel® Quartus® Prime project, or File > Open Project to open an existing Intel® Quartus® Prime project. The wizard prompts you to specify a device. In the Intel® Quartus® Prime Standard Edition software, this step is not required.
- In the IP Catalog (Tools > IP Catalog), locate and double-click RapidIO (IDLE1 up to 5.0 Gbaud) IP core to customize. The New IP Variation window appears.
- Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file with one of the following names:
- <your_ip> .ip (When you generate Intel® Arria® 10 and Intel® Cyclone® 10 GX variations in the Intel® Quartus® Prime Pro Edition software.)
- <your_ip> .qsys (When you generate any device variations in the Intel® Quartus® Prime Standard Edition software.)
- Click Create/OK. The parameter editor appears.
- Specify the parameters and options for your IP variation in the parameter editor, including one or more of the following:
- Optionally select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
- Specify parameters defining the IP core functionality, port configurations, and device-specific features.
- Specify options for processing the IP core files in other EDA tools.
- Click Generate HDL. The Generation dialog box appears.
- Specify output file generation options, and then click Generate. The software generates a testbench for your IP core when you create a simulation model. The synthesis and simulation files generate according to your specifications.
Note:
If you click Generate > Generate Testbench System, and then click Generate, the Intel® Quartus® Prime software generates a testbench framework. However, the resulting testbench is composed of BFM stubs and does not exercise the RapidIO IP core in any meaningful way.
- To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
- Click Finish. Click Yes if prompted to add files representing the IP variation to your project. Optionally turn on the option to Automatically add Intel® Quartus® Prime IP Files to All Projects. Click Project > Add/Remove Files in Project to add IP files at any time.
Figure 4. Adding IP Files to ProjectNote:
For Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the generated .qsys file must be added to your project to represent IP and Platform Designer systems. For devices released prior to Intel® Arria® 10 and Intel® Cyclone® 10 GX devices, the generated .qip and .sip files must be added to your project for IP and Platform Designer systems.
- After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.