RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

4.2.2.1. General RapidIO Reset Signal Requirements

All reset signals can be asserted asynchronously to any clock. However, most reset signals must be deasserted synchronously to a specific clock.

The reset_n input signal can be asserted asynchronously, but must last at least one Avalon® system clock period and be deasserted synchronously to the rising edge of the Avalon® system clock.

Figure 10. Circuit to Ensure Synchronous Deassertion of reset_n

In systems generated by Platform Designer (Standard), this circuit is generated automatically. However, if your RapidIO IP core variation is not generated by Platform Designer (Standard), you must implement logic to ensure the minimal hold time and synchronous deassertion of the reset_n input signal to the RapidIO IP core.