RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

4.3.1. Features

The Physical layer has the following features:
  • Port initialization
  • Transmitter and receiver with the following features:
    • One, two, or four lane high-speed data serialization and deserialization (up to 5.0 Gbaud for 1x variations with 32-bit Atlantic interface; up to 5.0 Gbaud for 2x and 4x variations with 64-bit Atlantic interface)
    • Clock and data recovery (receiver)
    • 8B10B encoding and decoding
    • Lane synchronization (receiver)
    • Packet/control symbol assembly and delineation
    • Cyclic redundancy code (CRC) generation and checking on packets
    • Control symbol CRC-5 generation and checking
    • Error detection
    • Pseudo-random idle sequence generation
    • Idle sequence removal
  • Software interface (status/control registers)
  • Flow control (ackID tracking)
  • Time-out on acknowledgments
  • Order of retransmission maintenance and acknowledgments
  • ackID assignment
  • ackID synchronization after reset
  • Error management
  • Clock decoupling
  • FIFO buffer with level output port
  • Adjustable buffer sizes (4 KBytes to 32 KBytes)
  • Four transmission queues and four retransmission queues to handle packet prioritization
  • Can be configured to send link-request control symbols with cmd set to reset-device on fatal error
  • Attempts link-request link-response control symbol pair a configurable number of times before declaring fatal error, when a link-response is not received