RapidIO Intel FPGA IP User Guide

ID 683884
Date 9/15/2021
Public
Document Table of Contents

7. Testbench

The RapidIO IP core includes a demonstration testbench for your use when you create a simulation model. The purpose of the testbench is to provide examples of how to parameterize the IP core and how to use the Avalon® Memory-Mapped ( Avalon® -MM) and Avalon® Streaming ( Avalon® -ST) interfaces, to generate and process RapidIO transactions.

The demonstration testbench demonstrates the following functions:

  • Port initialization process
  • Transmission, reception, and acknowledgment of packets with 8 to 256 bytes of data payload
  • Support for 8-bit or 16-bit device ID fields
  • Reading from the software interface registers
  • Transmission and reception of multicast-event control symbols

The testbench generates and monitors transactions on the Avalon® -MM interfaces and Avalon® -ST interface.

The testbench generates MAINTENANCE, Input/Output, or DOORBELL transactions if you select the corresponding modules during parameterization of the IP core. If your IP core variation includes an Avalon® -ST pass-through interface, the testbench transfers Type 9 (Data Streaming) packets through that interface.

The testbench instantiates two symmetrical RapidIO IP core variations. One instance is the Device Under Test (DUT). The other instance acts as a RapidIO link partner for the RapidIO DUT module and is referred to as the sister_rio module. The sister_rio module responds to transactions initiated by the DUT and generates transactions to which the DUT responds. Bus functional models (BFM) are connected to the Avalon® -MM and Avalon® -ST interfaces of both the DUT and sister_rio modules, to generate transactions to which the link partner responds when appropriate, and to monitor the responses.

The following figure is a block diagram of the testbench in which all of the available Avalon® -MM interfaces are enabled. The two IP core modules communicate with each other using the RapidIO interface.

Figure 39. RapidIO IP Core Testbench

The testbench initiates the following transactions at the DUT and targets them to the sister_rio module:

  • SWRITE
  • NWRITE_R
  • NWRITE
  • NREAD
  • DOORBELL messages
  • MAINTENANCE writes and reads
  • MAINTENANCE port writes and reads
  • Type 9 (Data Streaming) transactions (using the Avalon® -ST interface)
Note: Your specific variation may not have all of the interfaces enabled. If an interface is not enabled, the transactions supported by that interface are not exercised by the testbench.

In addition, the RapidIO IP core modules implement the following features:

  • Multicast-event control symbol transmission and reception. The RapidIO IP core under test generates and transmits multicast-event control symbols in response to transitions on its multicast_event_tx input signal. The sister module checks that these control symbols arrive as expected.
  • Disabled destination ID checking, or not, selected at configuration.
  • NWRITE_R completion indication.
  • Transaction order preservation between DOORBELL transactions and I/O write transactions, or not, selected at configuration. If this feature is selected, the RapidIO IP core under test generates and transmits DOORBELL and write transactions. The testbench checks that the transaction packets arrive on the link in the expected order.

The figure illustrates the system specified in Verilog HDL in the testbench connections file (<design_name>_hookup.iv in variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX, and in the main testbench file <design_name > _altera_rapidio_<version>.tb in Intel® Arria® 10 and Intel® Cyclone® 10 GX variations).

Activity across the Avalon® -MM interfaces is generated and checked by running tasks that are defined in the bus functional models (BFMs). In variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX, these models are implemented in the following files:

  • <design_name>_avalon_bfm_master.v
  • <design_name>_avalon_bfm_slave.v

In variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX, the file <design_name>_tb.v implements the code that performs the test transactions.

In Intel® Arria® 10 and Intel® Cyclone® 10 GX variations, the BFMs, the connections, and the test transaction generation are integrated in the main testbench file <design_name > _altera_rapidio_<version>.tb.

The code that performs the test transactions performs a reset and initialization sequence necessary for the DUT and sister_rio IP cores to establish a link and exchange packets.