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1. About the RapidIO Intel FPGA IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Signals
6. Software Interface
7. Testbench
8. Platform Designer (Standard) Design Example
9. RapidIO Intel FPGA IP User Guide Archives
10. Document Revision History for the RapidIO Intel® FPGA IP User Guide
A. Initialization Sequence
B. Porting a RapidIO Design from the Previous Version of Software
2.1. Installing and Licensing Intel® FPGA IP Cores
2.2. Generating IP Cores
2.3. IP Core Generation Output ( Intel® Quartus® Prime Standard Edition)
2.4. RapidIO IP Core Testbench Files
2.5. Simulating IP Cores
2.6. Integrating Your IP Core in Your Design
2.7. Specifying Timing Constraints
2.8. Compiling the Full Design and Programming the FPGA
2.9. Instantiating Multiple RapidIO IP Cores
2.6.1. Calibration Clock
2.6.2. Dynamic Transceiver Reconfiguration Controller
2.6.3. Transceiver Settings
2.6.4. Adding Transceiver Analog Settings for Arria II GX, Arria II GZ, and Stratix IV GX Variations
2.6.5. External Transceiver PLL
2.6.6. Transceiver PHY Reset Controller for Intel® Arria® 10 and Intel® Cyclone® 10 GX Variations
2.9.1. Clock and Signal Requirements for Arria® V, Cyclone® V, and Stratix® V Variations
2.9.2. Clock and Signal Requirements for Arria II GX, Arria II GZ, Cyclone IV GX, and Stratix IV GX Variations
2.9.3. Correcting the Synopsys Design Constraints File to Distinguish RapidIO IP Core Instances
2.9.4. Sourcing Multiple Tcl Scripts for Variations other than Intel® Arria® 10 and Intel® Cyclone® 10 GX
6.2.1. Capability Registers (CARs)
6.2.2. Command and Status Registers (CSRs)
6.2.3. Maintenance Interrupt Control Registers
6.2.4. Receive Maintenance Registers
6.2.5. Transmit Maintenance Registers
6.2.6. Transmit Port-Write Registers
6.2.7. Receive Port-Write Registers
6.2.8. Input/Output Master Address Mapping Registers
6.2.9. Input/Output Slave Mapping Registers
6.2.10. Input/Output Slave Interrupts
6.2.11. Transport Layer Feature Register
6.2.12. Error Management Registers
6.2.13. Doorbell Message Registers
7.1. Reset, Initialization, and Configuration
7.2. Maintenance Write and Read Transactions
7.3. SWRITE Transactions
7.4. NWRITE_R Transactions
7.5. NWRITE Transactions
7.6. NREAD Transactions
7.7. Doorbell Transactions
7.8. Doorbell and Write Transactions With Transaction Order Preservation
7.9. Port-Write Transactions
7.10. Transactions Across the Avalon® -ST Pass-Through Interface
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6.2.13. Doorbell Message Registers
The RapidIO IP core has registers accessible by the Avalon® -MM slave port in the Doorbell module. These registers are described in the following sections.
Address | Name | Used by |
---|---|---|
Doorbell Message Space | ||
0x00 | Rx Doorbell | External Avalon® -MM master that generates or receives doorbell messages. |
0x04 | Rx Doorbell Status | |
0x08 | Tx Doorbell Control | |
0x0C | Tx Doorbell | |
0x10 | Tx Doorbell Status | |
0x14 | Tx Doorbell Completion | |
0x18 | Tx Doorbell Completion Status | |
0x1C | Tx Doorbell Status Control | |
0x20 | Doorbell Interrupt Enable | |
0x24 | Doorbell Interrupt Status |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
LARGE_SOURCE_ID (MSB) | [31:24] | RO | Reserved if the system does not support 16-bit device ID. | 8'b0 |
MSB of the DOORBELL message initiator device ID if the system supports 16-bit device ID. | ||||
SOURCE_ID | [23:16] | RO | Device ID of the DOORBELL message initiator | 8'b0 |
INFORMATION (MSB) | [15:8] | RO | Received DOORBELL message information field, MSB | 8'b0 |
INFORMATION (LSB) | [7:0] | RO | Received DOORBELL message information field, LSB | 8'b0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:8] | RO | Reserved | 24’b0 |
FIFO_LEVEL | [7:0] | RO | Shows the number of available DOORBELL messages in the Rx FIFO. A maximum of 16 received messages is supported. | 8'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:2] | RO | Reserved | 30'h0 |
PRIORITY | [1:0] | RW | Request Packet’s priority. 2’b11 is not a valid value for the priority field. An attempt to write 2’b11 to this field will be overwritten as 2’b10. | 2'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
LARGE_DESTINATION_ID (MSB) | [31:24] | RO | Reserved if the system does not support 16-bit device ID. | 8'h0 |
RW | MSB of the targeted RapidIO processing element device ID if the system supports 16-bit device ID. | |||
DESTINATION_ID | [23:16] | RW | Device ID of the targeted RapidIO processing element | 8'h0 |
INFORMATION (MSB) | [15:8] | RW | MSB information field of the outbound DOORBELL message | 8'h0 |
INFORMATION (LSB) | [7:0] | RW | LSB information field of the outbound DOORBELL message | 8'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:24] | RO | Reserved | 8'h0 |
PENDING | [23:16] | RO | Number of DOORBELL messages that have been transmitted, but for which a response has not been received. There can be a maximum of 16 pending DOORBELL messages. | 8'h0 |
TX_FIFO_LEVEL | [15:8] | RO | The number of DOORBELL messages in the staging FIFO plus the number of DOORBELL messages in the Tx FIFO. The maximum value is 16. | 8'h0 |
TXCPL_FIFO_LEVEL | [7:0] | RO | The number of available completed Tx DOORBELL messages in the Tx Completion FIFO. The FIFO can store a maximum of 16. | 8'h0 |
Field61 | Bits | Access | Function | Default |
---|---|---|---|---|
LARGE_DESTINATION_ID | [31:24] | RO | Reserved if the system does not support 16-bit device ID. | 8'h0 |
MSB of the targeted RapidIO processing element device ID if the system supports 16-bit device ID. | ||||
DESTINATION_ID | [23:16] | RO | The device ID of the targeted RapidIO processing element. | 8'h0 |
INFORMATION | [15:8] | RO | MSB of the information field of an outbound DOORBELL message that has been confirmed as successful or unsuccessful. | 8'h0 |
INFORMATION | [7:0] | RO | LSB of the information field of an outbound DOORBELL message that has been confirmed as successful or unsuccessful. | 8'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:2] | RO | Reserved | 30'h0 |
ERROR_CODE | [1:0] | RO | This error code corresponds to the most recently read message from the Tx Doorbell Completion register. After software reads the Tx Doorbell Completion register, a read to this register should follow to determine the status of the message. 2'b00—Response DONE status 2'b01—Response with ERROR status 2'b10—Time-out error |
2'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:2] | RO | Reserved | 30'h0 |
ERROR | [1] | RW | If set, outbound DOORBELL messages that received a response with ERROR status, or were timed out, are stored in the Tx Completion FIFO. Otherwise, no error reporting occurs. | 1'h0 |
COMPLETED | [0] | RW | If set, responses to successful outbound DOORBELL messages are stored in the Tx Completion FIFO. Otherwise, these responses are discarded.18 | 1'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:3] | RO | Reserved | 29'b0 |
TX_CPL_OVERFLOW | [2] | RW | Tx Doorbell Completion Buffer Overflow Interrupt Enable | 1'h0 |
TX_CPL | [1] | RW | Tx Doorbell Completion Interrupt Enable | 1'h0 |
RX | [0] | RW | Doorbell Received Interrupt Enable | 1'h0 |
Field | Bits | Access | Function | Default |
---|---|---|---|---|
RSRV | [31:3] | RO | Reserved | 29'h0 |
TX_CPL_OVERFLOW | [2] | RW1C | Interrupt asserted due to Tx Completion buffer overflow. This bit remains set until at least one entry is read from the Tx Completion FIFO. After reading at least one entry, software should clear this bit. It is not necessary to read all of the Tx Completion FIFO entries. | 1'h0 |
TX_CPL | [1] | RW1C | Interrupt asserted due to Tx completion status | 1'h0 |
RX | [0] | RW1C | Interrupt asserted due to received messages | 1'h0 |
Related Information
61 The completed Tx DOORBELL message comes directly from the Tx Doorbell Completion FIFO.