F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Document Table of Contents

3.8.8. Run-time Reset Sequence—TX + RX

Figure 87. Run-time Reset Sequence—TX + RX

The figure above illustrates the following run-time TX - RX reset sequence:

  1. Assert tx_reset and rx_reset.
  2. tx_ready and rx_ready deassert, indicating that datapaths are no longer operational.
  3. tx_pll_locked and rx_is_lockedtodata deassert.
  4. tx_reset_ack and rx_reset_ack assert, indicating that the datapaths are fully in reset.
  5. You then deassert tx_reset and rx_reset.
  6. tx_pll_locked asserts as the PLL locks to the reference clock.
  7. rx_is_lockedtoref asserts as the CDR locks to the reference clock.
  8. rx_is_lockedtoref deasserts and rx_is_lockedtodata asserts as the CDR locks to the recovered data.
  9. tx_ready and rx_ready assert, indicating that the TX and RX datapaths are ready for use.