F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.8.6. Run-time Reset Sequence—TX

Figure 85. Run-time Reset Sequence—TX

The figure above illustrates the following run-time TX reset sequence:39

  1. Assert tx_reset.
  2. tx_ready deasserts, indicating that the TX datapath is no longer operational.
  3. tx_pll_locked deasserts.
  4. tx_reset_ack asserts, indicating that the TX datapath is fully in reset.
  5. You then deassert tx_reset to bring TX out of reset.
  6. tx_pll_locked asserts as the TX PLL locks to the reference clock.
  7. tx_ready asserts.
39 All timing diagrams show relative signal behavior and the waves do not show actual durations in time.