F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Public

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4.2. IP Port List

The following table lists the ports for the IP; all ports are 1-bit wide.

Table 97.   F-Tile Reference and System PLL Clocks Intel® FPGA IP Port ListRefer to Port Connection Guidelines between F-Tile Reference and System PLL Clocks Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP for recommended connections.
Port Name Direction Description
FHT
in_refclk_fht_i Input FHT reference clock input port. Must be mapped to device reference clock pin. Maximum of 2 (i = 0 to 1) ports of this type.
out_fht_cmmpll_clk_i Output FHT common PLL output port. Must be connected to protocol IPs, connected to FHT building-block. There can be a maximum of 2(i = 0 to 1) ports of this type.
FGT and System PLL
in_refclk_fgt_i Input FGT and system PLL reference clock input port. Must be mapped to device reference clock pin. This reference clock port can be connected to FGT PMA, system PLL or both. There can be a maximum of 10 (i = 0 to 9) ports of this type.
avmm_clk Input

Avalon® memory-mapped interface clock. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off. Intel recommends 100 to 250 MHz for this clock.

avmm_reset Input

Avalon® memory-mapped interface reset. This port is only available when at least one of Refclk #i is active at and after device configuration is set as Off.

refclock_ready [2:0] Input
System PLL reference clock status control signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set as Off.
  • bit[0] is used to control system PLL #0 reference clock.
  • bit[1] is used to control system PLL #1 reference clock.
  • bit[2] is used to control system PLL #2 reference clock.

When system PLL #i is disabled, bit[i] can be any value and does not matter. When system PLL #i is enabled, after the reference clock is available, you must assert bit[i] to notify the system PLL to start locking to the incoming reference clock.

refclock_status Output
System PLL reference clock status signal. This port is only available when all the enabled system PLL's corresponding Refclk #i is active at and after device configuration are set to Off. After you assert the refclock_ready signal, the system PLL starts to phase-lock to the reference clock and outputs its status.
  • 1'b0: The reference clock is active and has an accurate frequency.
  • 1'b1: The reference clock is inactive, or has an inaccurate frequency.
You can also use the out_systempll_synthlock_i signal to check the system PLL lock status.
FGT
out_refclk_fgt_i Output FGT Refclk output port. Must be connected to protocol IPs, connected to FGT building-block. There can be a maximum of 10 (i = 0 to 9) ports of this type.
in_cdrclk_i Input Input port for FGT reference clock configured as CDR output. This must be connected to protocol IP output CDR port. There can be a maximum of 2 (i = 0 to 1) ports of this type.
out_cdrclk_i Output Output port for FGT reference clock configured as CDR output. This must be connected to one of two FGT reference clock pins that can be configured as CDR outputs. You must specify the location assignment in the Intel® Quartus® Prime Pro Edition software qsf settings file for correct functionality. There can be a maximum of 2 (i = 0 to 1) ports of this type.
out_coreclk_i Output

FGT reference clock output port for user logic. This port is only available when the corresponding Export Refclk #i for use in user logic is set to On. There can be a maximum of 10 (i = 0 to 9) ports of this type.

System PLL
out_systempll_clk_i Output Output port of system PLL. This must be connected to system PLL clock input of protocol IP. There can be a maximum of 3 (i = 0 to 2) ports of this type.
out_systempll_synthlock_i Output System PLL lock status port which indicates if system PLL is locked to incoming reference clock. There can be a maximum of 3 (i = 0 to 2) ports of this type. You can use this port as a status or debug signal.