F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Public

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3.6.3. Port Widths and Recommended Connections for tx/rx_coreclkin, tx/rx_clkout, and tx/rx_clkout2

Port Widths and Recommended Connections shows the port width and recommended connection for the following ports:

  • tx_clkout and rx_clkout
  • tx_clkout2 and rx_clkout2
  • tx_coreclkin and rx_coreclkin
Table 75.  Port Widths and Recommended ConnectionsRefer to Variables Defining Bits for the Interfacing Ports in Port and Signal Reference for variable definitions.
PMA Width Port Width for tx_clkout, tx_clkout2, tx_coreclkin,rx_clkout, rx_clkout2, rx_coreclkin Recommended Connection
8, 10, 16, 20, 32 1 * N
  • Connect tx_clkout [0] or tx_clkout2[0] to tx_coreclkin[N-1:0]
  • Connect rx_clkout [0] or rx_clkout2[0] to rx_coreclkin[N-1: 0]
64 2 * N
  • Connect tx_clkout [0] or tx_clkout2[0] to tx_coreclkin[2 * N-1 : 0]
  • Connect rx_clkout [0] or rx_clkout2[0] to rx_coreclkin[2*N-1: 0]
128 4 * N
  • Connect tx_clkout [0] or tx_clkout2[0] to tx_coreclkin[4 * N-1 : 0]
  • Connect rx_clkout [0] or rx_clkout2[0] to rx_coreclkin[4*N-1: 0]
Table 76.  Example with Number of PMA Lane = 1
PMA Width tx/rx_clkout/2 Port Width Recommended Connection
8, 10, 16, 20, 32 1
  • Connect tx_clkout or tx_clkout2 to tx_coreclkin
  • Connect rx_clkout or rx_clkout2 to rx_coreclkin
64 2
  • Connect tx_clkout[0] or tx_clkout2[0] to tx_coreclkin[1:0]
  • Connect rx_clkout[0] or rx_clkout2[0] to rx_coreclkin[1:0]
128 4
  • Connect tx_clkout[0] or tx_clkout2[0] to tx_coreclkin[3:0]
  • Connect rx_clkout[0] or rx_clkout2[0] to rx_coreclkin[3:0]
Table 77.  Example with Number of PMA Lanes = 4
PMA Width tx/rx_clkout/2 Port Width Recommended Connection
8, 10, 16, 20, 32 4
  • Connect tx_clkout[0] or tx_clkout2[0] to tx_coreclkin[3:0]
  • Connect rx_clkout[0] or rx_clkout2[0] to rx_coreclkin[3:0]
64 8
  • Connect tx_clkout[0] or tx_clkout2[0] to tx_coreclkin[7:0]
  • Connect rx_clkout[0] or rx_clkout2[0] to rx_coreclkin[7:0]
128 16
  • Connect tx_clkout[0] or tx_clkout2[0] to tx_coreclkin[15:0]
  • Connect rx_clkout[0] or rx_clkout2[0] to rx_coreclkin[15:0]