F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Public

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3.14.2.1.1. Direct Register Method Examples

The following examples demonstrate the direct register method to configure the FGT PMA.

TX Equalizer Co-efficients

To set the TX equalizer co-efficients:
  • Write the TX equalizer pre_tap_2 register (0x47830[18:16]) with valid value.
  • Write the TX equalizer pre_tap_1 register (0x47830[9:5]) with valid value.
  • Write the TX equalizer main_tap register (0x47830[15:10]) with valid value.
  • Write the TX equalizer post_tap_1 register (0x47830[4:0]) with valid value.

Mute TX Output

To mute TX output (make TX output 0v):
  • Set 0x41750[25:24] to 2’b11
To unmute TX output:
  • Set 0x41750[25:24] to 2’b00

Internal Serial Loopback

To enable internal serial loopback 40:
  • Set 0x41418[31] to 0x0
  • Set 0x41420[25] to 0x1
  • Set 0x41418[29] to 0x1
  • Set 0x41418[31] to 0x1
To disable internal serial loopback:
  • Set 0x41418[31] to 0x0
  • Set 0x41418[29] to 0x0
  • Set 0x41420[25] t0 0x0

Reverse Parallel Loopback

To enable the Reverse Parallel Loopback:
  • Write 0x1 to 0x41414[29]
  • Write 0x1 to 0x4141C[30]
  • Write 0x1 to 0x41418[31]
To disable the Reverse Parallel Loopback:
  • Write 0x0 to 0x41414[29]
  • Write 0x0 to 0x4141C[30]
  • Write 0x0 to 0x41418[31]

TX to RX Parallel Loopback

To enable the TX to RX Parallel Loopback:
  • Write 0x1 to 0x416A4[8]
  • Write 0x1 to 0x41418[31]
To disable the TX to RX Parallel Loopback:
  • Write 0x0 to 0x416A4[8]
  • Write 0x0 to 0x41418[31]

Polarity Inversion

TX polarity inversion40:
  • Write 0x1 to 0x41428[7]
TX polarity inversion revert back:
  • Write 0x0 to 0x41428[7]
RX polarity inversion:
  • Write 0x1 to 0x41428[6]
RX polarity inversion revert back:
  • Write 0x0 to 0x41428[6]

Measuring the Bit Error Rate (BER) with FGT PMAs

  1. Check that the RX link is ready for the desired lane:
    1. Read 0x814[31:16] to confirm that the corresponding lane's rx_cdr_locked2data = 1
  2. Assign the PRBS pattern value:
    1. For TX:
      1. Set valid values to 0x416AC[31:28]
    2. For RX:
      1. Set valid values to 0x41428[3:0]
    3. Valid values for PRBS pattern:
      • UDP : 0x0
      • PRBS7 : 0x1
      • PRBS9 : 0x2
      • PRBS11 : 0x3
      • PRBS13 : 0x4
      • PRBS15 : 0x5
      • PRBS23 : 0x6
      • PRBS28 : 0x7
      • PRBS31 : 0x8
      • QPRBS13 : 0x9
      • PRBS13Q : 0xa
      • PRBS31Q : 0xb
      • SSPR : 0xc
      • SSPR1 : 0xd
      • SSPRQ : 0xe
  3. BER Start:
    1. Write 0x1 to 0x416AC[23]
    2. Write 0x1 to 0x41424[26]
    3. Write 0x3 to 0x4176C[28:27]
    4. Write 0x3 to 0x415B4[19:18]
  4. BER Count:
    1. Read from 0x41444[31:0]
  5. BER Stop:
    1. Write 0x0 to 0x416AC[23]
    2. Write 0x0 to 0x41424[26]
    3. Write 0x0 to 0x4176C[28:27]
    4. Write 0x0 to 0x415B4[19:18]
  6. To check overflow, read 0x4143C[21]
  7. To clear the counter, toggle 0x415B4[19:18]:
    1. Write 0x3 to 0x415B4[19:18]
    2. Write 0x0 to 0x415B4[19:18]
40 The sequence is valid only when RX manual tuning is used (RX auto adaptation is bypassed). If RX auto adaptation is used, use the FGT attribute access method.