F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.2.4. FGT PMA Loopback Modes

The PHY contains multiple parallel, serial data, and clock loopbacks across PHY interfaces for BIST. These loopbacks provide support for multiple PHY configurations.

Figure 48. FGT PMA Loopback ModesThe IP parameter editor does not currently support the loopback modes. Use register settings to specify loopback modes.
  • A. PMA-Transmitter-to-Receiver Internal Serial Loopback: Loops back the transmitter pre-driver differential I/O signals to the midpoint of the receiver equalizer. The internal serial loopback path sets the CDR to recover data from the serializer instead of the receiver serial input pin. The transmitter buffer sends data normally, but the internal serial loopback takes the data before the buffer. It is implemented completely in the PMA and does not require any connector on the serial path.
  • B. PMA-Transmitter-to-Receiver Digital Parallel Loopback: Parallel loopback from the PMA transmit lane 64 bit data ports to the receive lane 64 bit data ports. In a digital parallel loopback path, the parallel data stream of the transmitter is looped back as the parallel data input stream for the receiver.
  • C. PMA-Receiver-to-Transmitter Reverse Parallel Loopback: Parallel loopback from the PMA receive lane 64 bit data ports to the transmit lane 64 bit data ports. The reverse parallel loopback path sets the transmitter buffer to transmit data fed directly from the CDR recovered data. From an external instrument, data is fed to the receiver buffer, and the deserialized parallel data stream of the receiver is looped back as the parallel data input stream for the transmitter.