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1. F-Tile Overview
2. F-Tile Architecture
3. Implementing the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
4. Implementing the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5. F-Tile PMA/FEC Direct PHY Design Implementation
6. Supported Tools
7. Debugging F-Tile Transceiver Links
8. F-Tile Architecture and PMA and FEC Direct PHY IP User Guide Archives
9. Document Revision History for the F-Tile Architecture and PMA and FEC Direct PHY IP User Guide
A. Appendix
2.1.1. FHT and FGT PMAs
2.1.2. 400G Hard IP and 200G Hard IP
2.1.3. PMA Data Rates
2.1.4. FEC Architecture
2.1.5. PCIe* Hard IP
2.1.6. Bonding Architecture
2.1.7. Deskew Logic
2.1.8. Embedded Multi-die Interconnect Bridge (EMIB)
2.1.9. IEEE 1588 Precision Time Protocol for Ethernet
2.1.10. Clock Networks
2.1.11. Reconfiguration Interfaces
2.2.1. PMA-to-Fracture Mapping
2.2.2. Determining Which PMA to Map to Which Fracture
2.2.3. Hard IP Placement Rules
2.2.4. IEEE 1588 Precision Time Protocol Placement Rules
2.2.5. Topologies
2.2.6. FEC Placement Rules
2.2.7. Clock Rules and Restrictions
2.2.8. Bonding Placement Rules
2.2.9. Preserving Unused PMA Lanes
2.2.2.1. Implementing One 200GbE-4 Interface with 400G Hard IP and FHT
2.2.2.2. Implementing One 200GbE-2 Interface with 400G Hard IP and FHT
2.2.2.3. Implementing One 100GbE-1 Interface with 400G Hard IP and FHT
2.2.2.4. Implementing One 100GbE-4 Interface with 400G Hard IP and FGT
2.2.2.5. Implementing One 10GbE-1 Interface with 200G Hard IP and FGT
2.2.2.6. Implementing Three 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.7. Implementing One 50GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.8. Implementing One 100GbE-1 and Two 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.9. Implementing Two 100GbE-1 and One 25GbE-1 Interfaces with 400G Hard IP and FHT
2.2.2.10. Implementing 100GbE-1, 100GbE-2, and 50GbE-1 Interfaces with 400G Hard IP and FHT
3.1. F-Tile PMA/FEC Direct PHY Intel® FPGA IP Overview
3.2. Designing with F-Tile PMA/FEC Direct PHY Intel® FPGA IP
3.3. Configuring the IP
3.4. Signal and Port Reference
3.5. Bit Mapping for PMA and FEC Mode PHY TX and RX Datapath
3.6. Clocking
3.7. Custom Cadence Generation Ports and Logic
3.8. Asserting Reset
3.9. Bonding Implementation
3.10. Independent Port Configurations
3.11. Configuration Registers
3.12. Configurable Intel® Quartus® Prime Software Settings
3.13. Configuring the F-Tile PMA/FEC Direct PHY Intel® FPGA IP for Hardware Testing
3.14. Hardware Configuration Using the Avalon® Memory-Mapped Interface
3.3.1. General and Common Datapath Options
3.3.2. TX Datapath Options
3.3.3. RX Datapath Options
3.3.4. RS-FEC (Reed Solomon Forward Error Correction) Options
3.3.5. Avalon® Memory Mapped Interface Options
3.3.6. Register Map IP-XACT Support
3.3.7. Example Design Generation
3.3.8. Analog Parameter Options
3.4.1. TX and RX Parallel and Serial Interface Signals
3.4.2. TX and RX Reference Clock and Clock Output Interface Signals
3.4.3. Reset Signals
3.4.4. RS-FEC Signals
3.4.5. Custom Cadence Control and Status Signals
3.4.6. TX PMA Control Signals
3.4.7. RX PMA Status Signals
3.4.8. TX and RX PMA and Core Interface FIFO Signals
3.4.9. PMA Avalon® Memory Mapped Interface Signals
3.4.10. Datapath Avalon® Memory Mapped Interface Signals
3.5.1. Parallel Data Mapping Information
3.5.2. TX and RX Parallel Data Mapping Information for Different Configurations
3.5.3. Example of TX Parallel Data for PMA Width = 8, 10, 16, 20, 32 (X=1)
3.5.4. Example of TX Parallel Data for PMA width = 64 (X=2)
3.5.5. Example of TX Parallel Data for PMA width = 64 (X=2) for FEC Direct Mode
3.8.1. Reset Signal Requirements
3.8.2. Power On Reset Requirements
3.8.3. Reset Signals—Block Level
3.8.4. Reset Signals—Descriptions
3.8.5. Status Signals—Descriptions
3.8.6. Run-time Reset Sequence—TX
3.8.7. Run-time Reset Sequence—RX
3.8.8. Run-time Reset Sequence—TX + RX
3.8.9. Run-time Reset Sequence—TX with FEC
5.1. Implementing the F-Tile PMA/FEC Direct PHY Design
5.2. Instantiating the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
5.3. Implementing a RS-FEC Direct Design in the F-Tile PMA/FEC Direct PHY Intel® FPGA IP
5.4. Instantiating the F-Tile Reference and System PLL Clocks Intel® FPGA IP
5.5. Enabling Custom Cadence Generation Ports and Logic
5.6. Connecting the F-Tile PMA/FEC Direct PHY Design IP
5.7. Simulating the F-Tile PMA/FEC Direct PHY Design
5.8. F-Tile Interface Planning
7.2.1. Modifying the Design to Enable F-Tile Transceiver Debug
7.2.2. Programming the Design into an Intel FPGA
7.2.3. Loading the Design to the Transceiver Toolkit
7.2.4. Creating Transceiver Links
7.2.5. Running BER Tests
7.2.6. Running Eye Viewer Tests
7.2.7. Running Link Optimization Tests
7.2.8. Checking FEC Statistics
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4.4. Guidelines for F-Tile Reference and System PLL Clocks Intel® FPGA IP Usage
You must adhere to the following guidelines to correctly use the F-Tile Reference and System PLL Clocks Intel® FPGA IP:
- The F-Tile Reference and System PLL Clocks Intel® FPGA IP must always connect to the F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs. You cannot compile or simulate the F-Tile Reference and System PLL Clocks Intel® FPGA IP as a standalone IP.
- Once the reference clock for the system PLL is up; it must be stable; it must be present throughout the device operation and must not go down. If you are not able to adhere to this, you must reconfigure the device. After the temporary loss of the system PLL reference clock, you may observe that the first try of device reconfiguration fails. If that happens, you should try to reconfigure the device a second time.
- You must connect the reference clock and system PLL output ports of F-Tile Reference and System PLL Clocks Intel® FPGA IP to input of F-Tile PMA/FEC Direct PHY Intel® FPGA IP as shown in Port Connection Guidelines between F-Tile Reference and System PLL Clocks Intel® FPGA IP and F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs.
- You must ensure the reference clock and system PLL frequencies specified in F-Tile Reference and System PLL Clocks Intel® FPGA IP match reference clock and system PLL frequencies specified in F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs. Any mismatch in frequency results in Intel® Quartus® Prime Pro Edition software Support-Logic Generation failure.
- You must enable at least one system PLL per F-tile because this is a requirement for F-tile configuration to pass successfully. Enabling at least one system PLL is required even when the data path is using PMA clocking mode. If your design has one system PLL enabled to be used for system PLL clocking, you do not need a separate system PLL for F-tile configuration. When you use the system PLL only for F-tile configuration (that is, when all lanes use the PMA clocking mode) the following guidelines apply:
- You must enable System PLL #0. If you enable System PLL #1 or System PLL #2, the Intel® Quartus® Prime Pro Edition software Support-Logic Generation step fails.
- The system PLL output must be unconnected. This is the only exception where you can leave the system PLL output unconnected. In all other scenarios you must always connect the system PLL output to F-Tile PMA/FEC Direct PHY Intel® FPGA IP or protocol IPs.
- If you are not using the FGT PMA, the reference clock to system PLL connection is not necessary (that is, you do not need to connect the reference clock); however, if you connect a reference clock, the configuration completes faster.
- If you are using the FGT PMA, the reference clock to system PLL connection is necessary (that is, you must connect the reference clock).
- When you instantiate multiple interfaces or protocol-based IP cores within a single F-tile, you must use only one instance of the F-Tile Reference and System PLL Clocks Intel® FPGA IP to configure the following:
- All reference clocks for the FGT PMA (up to 10) and the FHT PMA (up to 2) that are required to implement those multiple interfaces within a single F-tile.
- All FHT common PLLs (up to 2) that are required to implement those multiple interfaces within a single F-tile.
- All system PLLs (up to 3) that are required to implement those multiple interfaces within a single F-tile.
- All reference clocks for system PLLs (up to 8, shared with the FGT PMA) that are required to implement those multiple interfaces within a single F-tile.
All reference clock, system PLL and common PLL selection in the IP parameter editor are logical. The .qsf assignments map these logical selection to physical resources.
- Although system PLL reference clock source lists ten reference clocks (reference clock #0 to #9), only eight physical reference clocks can clock the system PLL. For example, you could select reference clock #10 as the system PLL reference clock source, but this must be physically mapped to FGT/System PLL reference clock location 0 to 7 by specifying the .qsf assignments.
- When you enable the FGT CDR Output (RX recovered clock output), you must physically map the corresponding FGT PMA to FGT Quad 2 or 3, and you must physically map the FGT CDR Output (RX recovered clock output) to the FGT reference clock location 8 or 9 (configured as output).
- The total number of FGT/system PLL reference clocks and FGT CDR clock out that are enabled must not exceed 10.
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