F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
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2.3.2.1.1. FGT Transmitter Buffer and Phase Generator

A simplified FGT transmitter buffer termination scheme is shown in the following figure.
Figure 45. Simplified TX Buffer Termination
  1. ZTX-DIFF-DC transmitter buffer output differential DC impedance is 90 Ω; 45 Ω single ended.

The transmitter buffer can be programmed to support the taps listed in the following table.

Table 17.  FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes
Note: Applicable for Intel Agilex® 7 F-tile devices with OPNs mentioned in Appendix A.1 .
Register Value QSF Parameter Cursor Rule

Increment and

Decrement Size

Minimum Default Maximum
pre_tap_2 txeq_pre_tap_2 C-2 0 0 +7 1.0
pre_tap_1 txeq_pre_tap_1 C-1 0 0 +15 1.0
main_tap txeq_main_tap C0 9 0 0

+55 10

1.0
post_tap_1 txeq_post_tap_1 C+1 0 0 +19 1.0
Table 18.  FGT Transmitter PMA Equalizer Parameters for NRZ and PAM4 Modes
Note: Applicable for Intel Agilex® 7 F-tile ES devices, excluding OPNs mentioned in Appendix A.1 .
Register Value Cursor Rule

Increment and

Decrement Size

Minimum Maximum
pre_tap_2 C-2 0 +7 1.0
pre_tap_1 C-1 0 +15 1.0
main_tap C0 11 0 +47 12 1.0
post_tap_1 C+1 0 +19 1.0
The transmitter buffer equalizer parameter combinations follow the rules shown below.
  • For Intel Agilex® 7 F-tile ES devices, excluding OPNs mentioned in Appendix A.1 :
    1. main_tap - 2×pre_tap_1 - 2×post_tap_1 ≥ 5
    2. (main_tap + 9 - 2×pre_tap_1 - pre_tap_2 - 2×post_tap_1) ÷ (main_tap + 9 -pre_tap_2 - 2×post_tap_1) > 0
    3. (main_tap + 9 - 2×pre_tap_1 - pre_tap_2 - 2×post_tap_1) ÷ (main_tap + 9 - 2×pre_tap_1 - pre_tap_2) > 0
    4. QSF: (txeq_main_tap + txeq_pre_tap_1 + txeq_pre_tap_2 + txeq_post_tap_1) ≤ 47
  • For Intel Agilex® 7 F-tile devices with OPNs mentioned in Appendix A.1 :
    1. main_tap - 2×pre_tap_1 - 2×post_tap_2 ≥ 13
    2. (main_tap + 1 - 2×pre_tap_1 - pre_tap_2 - 2×post_tap_1) ÷ (main_tap + 1 - pre_tap_2 - 2×post_tap_1) > 0
    3. (main_tap + 1 - 2×pre_tap_1 - pre_tap_2 - 2×post_tap_1) ÷ (main_tap + 1 - 2×pre_tap_1 - pre_tap_2) > 0
9 C0 = main_tap + 1 - pre_tap_1 -pre_tap_2 - post_tap_1 for Intel Agilex® 7 F-tile devices with OPNs mentioned in Appendix A.1 .
10 main_tap and txeq_main_tap maximum value for Intel Agilex® 7 F-tile devices with OPNs mentioned in Appendix A.1 .
11 C0 = main_tap + 9 - pre_tap_1 - pre_tap_2 - post_tap_1 for Intel Agilex® 7 F-tile ES devices, excluding OPNs mentioned in Appendix A.1 .
12 main_tap maximum value for Intel Agilex® 7 F-tile ES devices, excluding OPNs mentioned in Appendix A.1 .