F-Tile Architecture and PMA and FEC Direct PHY IP User Guide

ID 683872
Date 10/02/2023
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3.14.2.2. FGT Attribute Access Method

Using the FGT attribute access method, you update the FGT PMA registers to configure hardware with a specific sequence of commands.
For example, you can configure serial internal loopback, PRBS generator and verifier using the FGT attribute access method. The FGT attribute access method consists of 4 steps in a sequence as shown below:
  1. Write data value to LINK_MNG_SIDE_CPI_REGS register to assert a service request.
  2. Read PHY_SIDE_CPI_REGS register to confirm the request has been acknowledged and completed; if not, repeat this step.
  3. Write data value to LINK_MNG_SIDE_CPI_REGS register to deassert the service request.
  4. Read PHY_SIDE_CPI_REGS register to confirm the request in step 3 has been acknowledged; if not, repeat this step.
Table 92.  FGT Attribute Access Addresses for JTAG Master that Controls 16 channels
Channels LINK_MNG_SIDE_CPI_REGS Address PHY_SIDE_CPI_REGS Address
Channel 0 or 1 or 2 or 3 0x0009003c 0x00090040
Channel 4 or 5 or 6 or 7 0x0049003c 0x00490040
Channel 8 or 9 or 10 or 11 0x0089003c 0x00890040
Channel 12 or 13 or 14 or 15 0x00C9003c 0x00C90040
Table 93.  FGT Attribute Access Data Value 1
  Serial Loopback TX and RX PRBS Selection Polarity Setup BER Measurement Start/Stop Test
Data field[31:16]

Enable: 0x6

Disable: 0x0

PRBS7: 0x208

PRBS9: 0x249

PRBS11: 0x28A

PRBS13: 0x965

PRBS23: 0x2CB

PRBS31: 0x30C

QPRBS13: 0x34D

PRBS13Q: 0x820

PRBS31Q: 0x861

SSPR: 0x8A2

SSPR1: 0x8E3

SSPRQ: 0x924

Reverse: 0x1

Revert back: 0x0

0x14

Start: 0x20

Stop: 0x21

Option field [15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved

Lane number field[11:8] Use 0xFFFFC[1:0], 0x1FFFFC[1:0]… 0xFFFFFC[1:0] to read back logical lane 0, 1 until lane 15’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0x40 0x41

TX polarity: 0x65

RX polarity: 0x66

0x45 0x0F
Note: 0x0F is not equivalent to 0xF
Table 94.  FGT Attribute Access Data Value 2
  Get Status Error Number to Inject Enable Error Injection Read Results Finish BER Measurement
Data field[31:16]

0x0

0x[Error_Num]

0x23

0x0

0x0

Option field [15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved

Lane number field[11:8] Use 0xFFFFC[1:0], 0x1FFFFC[1:0]… 0xFFFFFC[1:0] to read back logical lane 0, 1 until lane 15’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0x49: Get Test status

0x0D: Get PMA status

0x42 0x0F
Note: 0x0F is not equivalent to 0xF
  • LSB: 0x4A
  • Middle: 0x4B
  • MSB: 0x4C
0x41
Table 95.  FGT Attribute Access Data Value 3
  RX CDR Clock
Data field[31:16]

Bit [31:30]: Lane ID to use as source for rx_cdr_divclk_link0

Bit [29]:

1'b1: Enable rx_cdr_divclk_link0

1'b0: Disable rx_cdr_divclk_link0

Bit [28:25]: Read only for GET command to return the lane ID source

0x0: rx_cdr_divclk_link0 is enabled with lane 0 as source

0x1: rx_cdr_divclk_link0 is enabled with lane 1 as source

0x2: rx_cdr_divclk_link0 is enabled with lane 2 as source

0x3: rx_cdr_divclk_link0 is enabled with lane 3 as source

0xF: rx_cdr_divclk_link0 is disabled

Bit [24:16]: Reserved

Option field[15:12]

Bit [15] SERVICE_REQ to indicate a request: 0 = no request, 1 = service requested.

Bit [14] RESET: 0 = not in reset, 1 = in reset.

Bit [13] SET_GET: 0 = GET parameters, 1 = SET parameters.

Bit [12]: reserved

Lane number field[11:8] Use 0xFFFFC[1:0], 0x1FFFFC[1:0]… 0xFFFFFC[1:0] to read back logical lane 0, 1 until lane 15’s physical lane number.
  • If return value is 2’b00, physical lane is 0
  • If return value is 2’b01, physical lane is 1
  • If return value is 2’b10, physical lane is 2
  • If return value is 2’b11, physical lane is 3
Opcode field[7:0] 0xB1
You can create a function to write data, or read to and from FGT attribute access addresses. The data is comprised of data field[31:16], option field[15:12], lane number field[11:8], and opcode field[7:0]. The following examples use the tcl process as shown below:
proc attribute_access {{data field} {option field} {lane number field} {opcode field}}
You can use any programming language to perform the read and writes. For the other FGT PMA lanes, refer to FGT Attribute Access Addresses for JTAG Master that Controls 16 channels for LINK_MNG_SIDE_CPI_REGS and PHY_SIDE_CPI_REGS, and refer to FGT Attribute Access Data Value 1 for lane number field information.