P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
Public
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4. Quick Start Guide

Using Intel® Quartus® Prime Pro Edition, you can generate a simple Endpoint (EP) DMA design example for the P-Tile Avalon® memory-mapped IP for PCI Express IP core.

The generated design example reflects the parameters that you specify. It automatically creates the files necessary to simulate and compile the design example in the Intel® Quartus® Prime Pro Edition software. You can download the compiled design example to the Intel® Stratix® 10 DX Development Board or Intel® Agilex™ Development Board to do hardware testing. To download to custom hardware, update the Intel® Quartus® Prime Settings File (.qsf) with the correct pin assignments.

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