P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
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2.1.1.1. Register Set

The registers in the DMA Controller are 512-bit wide to match the data path width of the Bursting Master's and Read Data Mover's Avalon® -MM Master. This allows the Read Data Mover to write a descriptor in a single cycle if desired.

Table 4.  Register Set of the DMA Controller
Offset Name Access Description
0x000 WDN R/W

write: descriptor for the Write Data Mover normal descriptor queue

read: readiness and fill level of the Write Data Mover normal descriptor queue

0x200 WDP R/W

write: descriptor for the Write Data Mover priority descriptor queue

read: readiness and fill level of the Write Data Mover priority descriptor queue

0x400 WS RO Write Data Mover status queue
0x600 WI R/W Write Data Mover interrupt control register
0x800 RDN R/W

write: descriptor for the Read Data Mover normal descriptor queue

read: readiness and fill level of the Read Data Mover normal descriptor queue

0xA00 RDP R/W

write: descriptor for the Read Data Mover priority descriptor queue

read: readiness and fill level of the Read Data Mover priority descriptor queue

0xC00 RS RO Read Data Mover status queue
0xE00 RI R/W Read Data Mover interrupt control register

For the data written to the descriptor queue registers, use the same format and content as the data on the corresponding Avalon® -ST interfaces of the Data Movers. The least significant of the application specific bits indicates whether an interrupt should be issued when processing of that descriptor completes. The data is written to the least significant 174 bits of the registers because the descriptors are 174-bit wide (refer to Descriptor Format for Data Movers for the descriptor format).

The DMA Controller double buffers the write-only queues so that the descriptors can be built one DWORD at a time if required, for example by a 32-bit host controller. The content of the register is transferred to the Data Movers' Avalon® -ST input when the most significant DWORD is written.

Attempting to write to a descriptor queue when the corresponding Data Mover's ready signal is not asserted causes the DMA Controller to assert its waitrequest signal until ready is asserted. You must make sure the Read Data Mover does not attempt to write to the same queue that it is processing while the queue is full, as that would lead to a deadlock. For more details on deadlocks, refer to the section Deadlock Risk and Avoidance.

You can find the status of the ready signal of a descriptor queue interface by checking the ready bit (bit [31]) of the queue registers. In addition, bits [7:0] of the queue registers indicate the approximate fill level of the queues. The other bits of the queue registers are set to 0.

Only the least significant DWORD of the WS and RS registers contains significant information. The other bits are set to 0.

The format and content of the status queues are identical to the corresponding Avalon® -ST interfaces of the Data Movers with the addition of bit 31 indicating that the queue is empty. Reading from one of the status queues when it is empty returns 512'h8000_0000.

The format of the WI and RI interrupt control registers is as follows: {enable, priority, reserved[414:0], msi_msg_data[15:0], reserved[15:0], msi_address[63:0]}.

The enable bit controls whether or not an MSI is sent. The priority bit specifies whether to use the priority queue to send the MSI. The MSI memory write TLP also uses the contents of the msi_msg_data and msi_address fields.

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