P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
Public
Download

2.1.3. BAR Interpreter

The Bursting Master module transforms PCIe memory read and write request packets received from the PCIe system into Avalon® -MM read and write transactions. The offset from the matching BAR is provided as the Avalon® -MM address, and the number of the matching BAR is provided in a conduit synchronously with the address.

Although these signals are in a conduit separate from the Avalon® -MM master interface, they are synchronous to it and can be treated as extensions of the address bus.

The BAR Interpreter simply concatenates the BAR number to the address bus to form a wider address bus that Platform Designer can now treat as a normal address bus and route to the various slaves connected to the BAR Interpreter.

Did you find the information on this page useful?

Characters remaining:

Feedback Message