P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
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3. Current Limitations of the Design Examples

In the 20.4 release of Intel® Quartus® Prime, the design examples for the P-Tile Avalon® -MM IP for PCIe have the following limitations:
  • The Endpoint DMA design example cannot handle 10-bit tags.
  • To enable the Gen4 x16 Endpoint DMA design example to meet timing requirements at 350 MHz, you need to manually enable all pipelinable locations in the Platform Designer Interconnect fabric (mm_interconnect). Here are the steps to enable the mm_interconnect pipeline stages:
    1. Open the generated design example in Platform Designer.
    2. Click on System, then Show System with Platform Designer Interconnect.
    3. Click on Show Pipelinable Locations.
    4. Go through each mm_interconnect_N and enable all pipelinable registers for both Command and Response.
    5. Generate the HDL for the design example.
  • Simulation is supported for the Endpoint design example in the 20.4 release of Intel® Quartus® Prime, but it is available for the VCS simulator only.

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