P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

3. Current Limitations of the Design Examples

In the 20.4 release of Intel® Quartus® Prime, the design examples for the P-Tile Avalon® -MM IP for PCIe have the following limitations:
  • The Endpoint DMA design example cannot handle 10-bit tags.
  • To enable the Gen4 x16 Endpoint DMA design example to meet timing requirements at 350 MHz, you need to manually enable all pipelinable locations in the Platform Designer Interconnect fabric (mm_interconnect). Here are the steps to enable the mm_interconnect pipeline stages:
    1. Open the generated design example in Platform Designer.
    2. Click on System, then Show System with Platform Designer Interconnect.
    3. Click on Show Pipelinable Locations.
    4. Go through each mm_interconnect_N and enable all pipelinable registers for both Command and Response.
    5. Generate the HDL for the design example.
  • Simulation is supported for the Endpoint design example in the 20.4 release of Intel® Quartus® Prime, but it is available for the VCS simulator only.
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