1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
3. Current Limitations of the Design Examples
In the 20.4 release of Intel® Quartus® Prime, the design examples for the P-Tile Avalon® -MM IP for PCIe have the following limitations:
- The Endpoint DMA design example cannot handle 10-bit tags.
- To enable the Gen4 x16 Endpoint DMA design example to meet timing requirements at 350 MHz, you need to manually enable all pipelinable locations in the Platform Designer Interconnect fabric (mm_interconnect). Here are the steps to enable the mm_interconnect pipeline stages:
- Open the generated design example in Platform Designer.
- Click on System, then Show System with Platform Designer Interconnect.
- Click on Show Pipelinable Locations.
- Go through each mm_interconnect_N and enable all pipelinable registers for both Command and Response.
- Generate the HDL for the design example.
- Simulation is supported for the Endpoint design example in the 20.4 release of Intel® Quartus® Prime, but it is available for the VCS simulator only.
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