P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
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4.5. Compiling the Design Example

  1. Navigate to <project_dir>/intel_pcie_ptile_avmm_0_example_design/ and open pcie_ed.qpf.
  2. If you select one of the supported development kits mentioned in the Generating the Design Example section, the necessary VID-related settings are included in the .qsf file of the generated design example.
  3. If you are using another Intel® Stratix® 10 DX development kit, check that appropriate VID-related assignments have been included in the .qsf file of your projec.t
  4. If you are using another Intel® Agilex™ development kit, check that appropriate VID-related assignments have been included in the .qsf file of your project.
  5. On the Processing menu, select Start Compilation.

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