2. Endpoint Design Example
This DMA design example includes a DMA Controller and an on-chip memory to exercise the Data Movers.
The design example also connects the Bursting Master (in non-bursting mode) to the on-chip memory to allow high-throughput transfers should the host or some other component of the PCIe system be capable of initiating such transfers (e.g. a Root Complex with a DMA engine).
The on-chip memory that the Data Movers and the Bursting Master connect to is a dual-port memory to allow full-duplex data movement.
The Bursting Master connects to a BAR Interpreter module, which combines the address and BAR number and allows the Bursting Master to control the DMA Controller. The BAR Interpreter also connects the Bursting Master to the dual-port memory.
|DMA||0x0 - 0x0FFFF||0|
|MEM0.s1||0x20000 - 0x27FFF||2|
|MEM0.s2||0x28000 - 0x2FFFF||4|
The design example is generated dynamically based on the selected variation of the P-Tile Avalon® -MM IP for PCIe. However, some of the user’s parameter selections may need to be overwritten to ensure proper functionality. A warning appears when such a need arises.
In the 20.4 release of Intel® Quartus® Prime, the only variation supported is the DMA variation. This variation instantiates the Bursting Master (in non-bursting mode), Read Data Mover and Write Data Mover. Software sends instructions via the Bursting Master to the Read or Write Data Movers to initiate DMA Reads or Writes to the system memory. The BAR Interpreter, on-chip memory and DMA Controller are also included.
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