P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

Download PDF
ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

2. Endpoint Design Example

This DMA design example includes a DMA Controller and an on-chip memory to exercise the Data Movers.

The design example also connects the Bursting Master (in non-bursting mode) to the on-chip memory to allow high-throughput transfers should the host or some other component of the PCIe system be capable of initiating such transfers (e.g. a Root Complex with a DMA engine).

The on-chip memory that the Data Movers and the Bursting Master connect to is a dual-port memory to allow full-duplex data movement.

The Bursting Master connects to a BAR Interpreter module, which combines the address and BAR number and allows the Bursting Master to control the DMA Controller. The BAR Interpreter also connects the Bursting Master to the dual-port memory.

The following table shows the address and BAR mapping that the BAR Interpreter in this design example uses:
Table 2.  Address and BAR Map for the BAR Interpreter
Resource Address Range BAR
DMA 0x0 - 0x0FFFF 0
MEM0.s1 0x20000 - 0x27FFF 2
MEM0.s2 0x28000 - 0x2FFFF 4
Figure 1. DMA Design Example for Endpoint

The design example is generated dynamically based on the selected variation of the P-Tile Avalon® -MM IP for PCIe. However, some of the user’s parameter selections may need to be overwritten to ensure proper functionality. A warning appears when such a need arises.

In the 20.4 release of Intel® Quartus® Prime, the only variation supported is the DMA variation. This variation instantiates the Bursting Master (in non-bursting mode), Read Data Mover and Write Data Mover. Software sends instructions via the Bursting Master to the Read or Write Data Movers to initiate DMA Reads or Writes to the system memory. The BAR Interpreter, on-chip memory and DMA Controller are also included.

Note: Beginning with the 17.1 release, the Intel® Quartus® Prime Pro Edition software dynamically generates design examples for the parameters you specify in the parameter editor. Consequently, the Intel® Quartus® Prime Pro Edition installation directory no longer provides static design examples for Intel® Stratix® 10 devices. Static design examples are available for earlier device families, including Intel® Arria® 10 and Intel® Cyclone® 10 devices.
Level Two Title