P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

4.3. Generating the Design Example

Figure 6. Design Example Generation Procedure
  1. In the Intel® Quartus® Prime Pro Edition software, create a new project (File → New Project Wizard).
  2. Specify the Directory Name, and Top-Level Entity.
  3. For Project Type, accept the default value, Empty project. Click Next.
  4. For Add Files click Next.
  5. For Family, Device & Board Settings under Family, select Intel® Agilex™ or Intel® Stratix® 10 .
  6. If you select Intel® Stratix® 10 in the last step, select Stratix 10 DX in the Device pull-down menu.
  7. Select the Target Device for your design.
  8. Click Finish.
  9. In the IP Catalog locate and add the Intel P-Tile Avalon® -MM IP for PCI Express* .
  10. In the New IP Variant dialog box, specify a name for your IP. Click Create.
  11. On the Top-Level Settings and PCIe* Settings tabs, specify the parameters for your IP variation. For example, select Endpoint for the EP variant.
  12. On the Example Designs tab, make the following selections:
    1. For Example Design Files, turn on the Synthesis option. If you do not need these synthesis files, leaving the corresponding option turned off significantly reduces the example design generation time.
    2. For Generated HDL Format, only Verilog is available in the current release.
    3. For Target Development Kit, select the appropriate option. For the current release, the supported development kits are:
      • Intel® Stratix® 10 DX P-Tile ES1 FPGA Development Kit
      • Intel® Agilex™ F-Series P-Tile ES0 FPGA Development Kit
  13. Select Generate Example Design to create a design example that you can compile and download to hardware. If you select one of the P-Tile development boards, the device on that board overwrites the device previously selected in the Intel® Quartus® Prime project if the devices are different. When the prompt asks you to specify the directory for your example design, you can accept the default directory, <project_dir>/intel_pcie_ptile_avmm_0_example_design, or choose another directory.
    Figure 7. Example Designs Tab
  14. Click Finish. You may save your .ip file when prompted, but it is not required to be able to use the example design.
  15. Open the example design project.
  16. Compile the example design project to generate the .sof file for the complete example design. This file is what you download to a board to perform hardware verification.
  17. Close your example design project.
Note: You cannot change the PCIe pin allocations in the Intel® Quartus® Prime project. However, to ease PCB routing, you can take advantage of the lane reversal and polarity inversion features supported by this IP.
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