P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public
Document Table of Contents
Document Table of Contents x
1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
2. Endpoint Design Example x
2.1. Block Descriptions 2.2. Programming Model for the Design Example 2.3. Descriptor Format for the Design Example 2.4. DMA Operations Using the Design Example
2.1. Block Descriptions x
2.1.1. DMA Controller 2.1.2. Avalon-MM Address to PCIe Address Mapping 2.1.3. BAR Interpreter
2.1.1. DMA Controller x
2.1.1.1. Register Set 2.1.1.2. Deadlock Risk and Avoidance 2.1.1.3. Interrupts 2.1.1.4. Using the DMA Controller
2.4. DMA Operations Using the Design Example x
2.4.1. Read DMA Example 2.4.2. Write DMA Example
4. Quick Start Guide x
4.1. Design Components 4.2. Directory Structure 4.3. Generating the Design Example 4.4. Simulating the Design Example 4.5. Compiling the Design Example 4.6. Installing the Linux Kernel Driver 4.7. Running the Endpoint Design Example Application
1. Design Example Overview
2. Endpoint Design Example
3. Current Limitations of the Design Examples
4. Quick Start Guide
5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives
A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2022.03.28 21.1 4.0.0 Added a note to the Running the Endpoint Design Example Application section stating that the refclk switch on the Intel® Stratix® 10 DX FPGA Development Kit or the Intel® Agilex™ FPGA Development Kit must be set to the OFF position to select the common refclk from the PCIe Edge Connector for PCIe link stability.
2021.03.29 21.1 4.0.0 Added a note to the Design Example Overview section stating that the P-Tile Avalon® Memory-mapped IP for PCI Express will not be available in future releases of Intel® Quartus® Prime.
2020.12.14 20.4 4.0.0 Removed the Root Port design example as it is not supported in this release of Intel® Quartus® Prime.
2020.07.10 20.2 3.0.0

Added the Platform Designer view of the x8 Endpoint DMA design example.

Added the Root Port design example description.
2020.04.20 20.1 2.0.0 Updated the configurations supported by the Endpoint design example of the P-Tile Avalon® Memory Mapped IP for PCIe.
2019.12.16 19.4 1.1.0 Initial release.
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