P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022

4.1. Design Components

The available design example is for an Endpoint with a single function. This DMA design example includes a DMA Controller and an on-chip memory to exercise the Data Movers in the P-Tile Avalon-MM IP for PCI Express.

Figure 4. Block Diagram for the Platform Designer Avalon® -MM with DMA Design Example