P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

ID 683853
Date 3/28/2022
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2.1.1. DMA Controller

The DMA Controller in this example design consists of six addressable queues: two write-only queues and one read-only queue each for the Read Data Mover and the Write Data Mover. In addition, the DMA Controller has two MSI control registers for each Data Mover module.

The write-only queues directly feed into the Data Movers’ normal and priority descriptor queues. The read-only queues read directly from the Data Movers’ status queues.

The MSI control registers control whether MSI generation is enabled and defines the address and data to be used for the MSI.

The example design uses p<n>_app_clk generated from the coreclkout_hip clock.

Note: The P-Tile Avalon® -MM IP core does not include an internal DMA Controller. You can use the DMA Controller included in the example design that you can generate, or provide your own DMA Controller.

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